PL123E-09HSC PhaseLink Corp., PL123E-09HSC Datasheet
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PL123E-09HSC
Manufacturer Part Number
PL123E-09HSC
Description
Manufacturer
PhaseLink Corp.
Datasheet
1.P123E-09H.pdf
(10 pages)
Specifications of PL123E-09HSC
Case
SOP16
Date_code
08+
FEATURES
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/9/08 Page 1
REF
Frequency Range 10MHz to 220MHz
Zero input - output delay.
Low Output to Output Skew
Optional Drive Strength:
2.5V or 3.3V, ±10% operation.
Available in 16-Pin SOP or TSSOP packages
S1
S2
Standard (8mA) PL123E-09
High (12mA)
PLL
Selector
Inputs
PL123E-09H
Mux
DESCRIPTION
The PL123E-09 (-09H for High Drive) is a high per-
formance, low skew, low jitter zero delay buffer de-
signed to distribute high speed clocks. It has two low-
skew output banks, of 4 outputs each, that are syn-
chronized with the input. Control of the two banks of
outputs is achieved by using the S1 and S2 inputs as
shown in the Selector Definition table on page 2.
The synchronization is established via CLKOUT feed
back to the input of the PLL. Since the skew between
the input and output is less than 100ps, the device
acts as a zero delay buffer. The input output propaga-
tion delay can be advanced or delayed by adjusting the
load on the CLKOUT pin.
These parts are not intended for 5V input-tolerant ap-
plications.
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Low Skew Zero Delay Buffer
(Preliminary)
CLKA1
CLKA2
CLKB1
CLKB2
GND
VDD
REF
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1