PLL702-01XC PhaseLink Corp., PLL702-01XC Datasheet
PLL702-01XC
Manufacturer Part Number
PLL702-01XC
Description
Manufacturer
PhaseLink Corp.
Specifications of PLL702-01XC
Case
SSOP28
Date_code
08+
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PLL702-01XC-R
Manufacturer:
PHASELINK
Quantity:
20 000
FEATURES
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DESCRIPTION
The PLL702-01 is a low cost, low jitter, and high
performance clock synthesizer for generic PowerPC based
applications. It provides one CPU clock, three ASIC
outputs, one PCI output, and a selectable 48, 30 or 12MHz
(USB) output. The user can choose between 9 different
CPU clock frequencies, while the ASIC output can be
identical or half of the CPU frequency. Low EMI Spread
Spectrum Technology is available for the CPU, ASIC and
PCI clocks. The CPU drive strength is user selectable from
100% to 67%. All frequencies are generated from a single
low cost 14.31818MHz crystal. The CPU and ASIC clock
can be driven from an independent 2.5V power supply.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
1 CPU Clock output with selectable frequencies (50,
66, 75, 80, 83, 90, 100,125 or 133 MHz).
1 ASIC output clock (at CPU clock or CPU clock ÷ 2).
2 ASIC output clocks (at CPU clock) w/ output enable.
1 PCI output clock w/ output enable
1 Selectable 48, 30 or 12MHz (USB) output.
Selectable Spread Spectrum (SST) for EMI reduction
on ASIC and CPU.
PowerPC compatible output and drive CPU Clock.
Selectable reduced 67% drive strength on CPU Clock
Advanced, low power, sub-micron CMOS processes.
14.31818MHz fundamental crystal input.
3.3V and/or 2.5V operation.
Available in 28-Pin 209mil SSOP (QSOP)
CLK_SEL(0:1)
USB_SEL
ASIC1_SEL
SSC(0:1)
PCI_SEL
XOUT
XIN
Clock Generator for PowerPC Based Applications
XTAL
OSC
.
Control
Control
Logic
Logic
SST
PLL
PLL
PIN ASSIGNMENT (28 pin SSOP)
FREQUENCY TABLES
Notes:
CPU=133MHz, it implements 130.9MHz to meet Power PC clock AC Timing Specification.
* PCI_SEL=1 sets the Tri-state (output disabled) mode of the output.
CLK_SEL1
M
M
M
0
0
0
1
1
1
ASIC2_OE
PCI_OE
When CPU=90MHz, it implements 88.88MHz to meet PCI=33.3MHz/66.6MHz; When
DIV 2
XOUT / ASIC2_OE*^
CLK_SEL0
USB / USB_SEL*
Note :
CPUDRV_SEL ^
PCI / PCI_SEL*
M
M
M
0
1
0
1
0
1
VDD_ASIC2
GND_USB
VDD_ANA
VDD_USB
VDD_DIG
VDD_PC I
GND_PCI
o
^: Internal pull-up resistor
ASIC2 A
ASIC2 B
: Selectable reduced drive
strength
XIN
(MHz)
www.phaselink.com
CPU
100
125
133
50
66
75
80
83
90
T
T
10
11
12
13
14
1
2
3
4
5
6
7
8
9
ASIC1_SEL
100
125
133
50
66
75
80
83
90
=1
ASIC1 (MHz)
PLL702-01
28
27
26
25
24
23
22
21
20
19
18
17
16
15
USB
CPU_CLK
ASIC1
ASIC2(A:B)
PCI
ASIC1_SEL
*: Bi-directional pin
T
: Tri-level input
37.5
41.5
62.5
66.5
25
33
40
45
50
=0
Rev 07/18/05 Page 1
CLK_SEL0
CLK_SEL1
SSCO
SSC1
GND_ANA
GND_CP U
CP
VDD_CP U
VDD_ASIC1
ASIC1
GND_ASIC 1
ASIC1_SEL ^
GND_DIG
GND_ASIC2
U
o
^
^
ASIC2
(MHz)
T
T
100
125
133
50
66
75
80
83
90
PCI_SEL
62.5
66.7
62.5
66.7
66.7
66.7
66.7
62.5
65.5
=0
PCI* (MHz)
PCI_SEL
31.25
33.35
31.25
33.35
33.35
33.35
33.35
31.25
32.75
=M
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