FM3164-STR Ramtron, FM3164-STR Datasheet - Page 8

• Manufacturer Part Number: FM3164-STR
• Description: case, leaded, supervisor, reflow, soic, supply, process, max, ram, Interface ICs, package, compatible, voltage, memor...
• Manufacturer: Ramtron

Calibration
When the CAL bit in a register 00h is set to 1, the
clock enters calibration mode. In calibration mode,
the CAL/PFO output pin is dedicated to the
calibration function and the power fail output is
temporarily unavailable. Calibration operates by
applying a digital correction to the counter based on
the frequency error. In this mode, the CAL/PFO pin
is driven with a 512 Hz (nominal) square wave. Any
measured deviation from 512 Hz translates into a
timekeeping error. The user converts the measured
error in ppm and writes the appropriate correction
value to the calibration register. The correction
factors are listed in the table below. Positive ppm
errors require a negative adjustment that removes
pulses. Negative ppm errors require a positive
correction that adds pulses. Positive ppm adjustments
have the CALS (sign) bit set to 1, where as negative
ppm adjustments have CALS = 0. After calibration,
the clock will have a maximum error of
or
temperature.
Calibration Adjustments
Rev. 2.3
Oct. 2006
10
11
12
13
0
1
2
3
4
5
6
7
8
9
0.09 minutes per month at the calibrated
Layout for Surface Mount Crystal
(red = top layer, green = bottom layer)
512.0000
511.9989
511.9967
511.9944
511.9922
511.9900
511.9878
511.9856
511.9833
511.9811
511.9789
511.9767
511.9744
511.9722
Measured Frequency Range
Min
Positive Calibration for slow clocks: Calibration will achieve
VDD
SCL
SDA
X2
X1
PFI
VBAK
511.9989
511.9967
511.9944
511.9922
511.9900
511.9878
511.9856
511.9833
511.9811
511.9789
511.9767
511.9744
511.9722
511.9700
Max
2.17 ppm
Error Range (PPM)
10.86
15.20
19.54
23.88
28.22
32.56
36.90
41.24
45.58
49.92
54.26
2.18
6.52
Min
0
10.85
15.19
19.53
23.87
28.21
32.55
36.89
41.23
45.57
49.91
54.25
58.59
The calibration setting is stored in FRAM so is not
lost should the backup source fail. It is accessed with
bits CAL.4-0 in register 01h. This value only can be
written when the CAL bit is set to a 1. To exit the
calibration mode, the user must clear the CAL bit to a
0. When the CAL bit is 0, the CAL/PFO pin will
revert to the power fail output function.
Layout Requirements
The X1 and X2 crystal pins employ very high
impedance circuits and the oscillator connected to
these pins can be upset by noise or extra loading. To
reduce RTC clock errors from signal switching noise,
a guard ring must be placed around these pads and
the guard ring grounded. SDA and SCL traces should
be routed away from the X1/X2 pads. The X1 and X2
trace lengths should be less than 5 mm. The use of a
ground plane on the backside or inner board layer is
preferred. See layout example. Red is the top layer,
green is the bottom layer.
2.17
6.51
Max
Layout for Through Hole Crystal
(red = top layer, green = bottom layer)
2.17 PPM after calibration
Program Calibration Register to:
VDD
SCL
SDA
X2
X1
PFI
VBAK
000000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
FM3104/16/64/256
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