853S057AGILF IDT, 853S057AGILF Datasheet - Page 7

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853S057AGILF

Manufacturer Part Number
853S057AGILF
Description
Clock Drivers & Distribution
Manufacturer
IDT
Datasheet

Specifications of 853S057AGILF

Product Category
Clock Drivers & Distribution
Rohs
yes
Part # Aliases
ICS853S057AGILF
ICS853S057I Data Sheet
Application Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how the differential input can be wired to accept
single-ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock swing
is only 2.5V and V
0.609.
Recommendations for Unused Input Pins
Inputs:
CLK/nCLK Inputs
For applications not requiring the use of the differential input, a 1kΩ
resistor should be tied from nCLK to V
Single-ended LVPECL Control Pins
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
ICS853S057AGI REVISION A MAY 16, 2012
CC
= 3.3V, V_REF should be 1.25V and R2/R1 =
CC
.
CC
/2 is
7
4:1, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL CLOCK DATA MULTIPLEXER
Figure 1. Single-Ended Signal Driving Differential Input
Single Ended Clock Input
C1
0.1u
V_REF
©2012 Integrated Device Technology, Inc.
R1
1K
R2
1K
V
CC
CLKx
nCLKx

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