IS49NLC36160-25EBL ISSI, IS49NLC36160-25EBL Datasheet - Page 15

• Manufacturer Part Number: IS49NLC36160-25EBL
• Description: DRAM 576M, x36, 400Mhz RLDRAM2
• Manufacturer: ISSI

Specifications of IS49NLC36160-25EBL

• Rohs: yes
• Organization: 16 M x 36
• Package / Case: FBGA-144
• Memory Size: 576 Mbit
• Maximum Clock Frequency: 400 MHz
• Access Time: 2.5 ns
• Supply Voltage - Max: 2.63 V
• Supply Voltage - Min: 2.38 V
• Maximum Operating Current: 380 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT

IS49NLC96400,IS49NLC18320,IS49NLC36160
The Mode Register Set command stores the data for controlling the various operating modes of the memory using address inputs
A0-A17 as mode registers. During the MRS command, the cycle time and the read/write latency of the memory can be selected from
different configurations. The MRS command also programs the memory to operate in either Multiplexed Address Mode or Non-
multiplexed Address Mode. In addition, several features can be enabled using the MRS command. These are the DLL, Drive
Impedance Matching, and On-Die Termination (ODT). t
the picture above in both Multiplexed and Non-multiplexed mode.
Mode Register Diagram (Non-multiplexed Address Mode)
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00F, 12/4/2012
Address
A10-17
Field
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A2
A10-A17 must be set to zero; A18-An are "Don't cares."
A6 not used in MRS.
BL = 8 is not available.
DLL RESET turns the DLL off.
±30 % temperature variation.
t
The minimum tRC is typically 3 cycles, except in the case of a WRITE followed by a READ to the same bank. In this instance the minimum t
tCK must be met to use this configuration. For tCK values, please refer to AC Electrical Characteristics table.
0
0
0
0
1
1
1
1
RC
< 20ns in any configuration is only available with -25E and -18 speed grades.
M10-17
Mode Register
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
A1
0
0
1
1
0
0
1
1
Config
ODT
NA
DLL
AM
IM
A0
0
BL
0
1
0
1
0
1
0
1
1
2
Configuration
1
Read/Write Latency and Cycle Time Configuration
Reserved
Reserved
3
(Default)
4
1
2
3
5
3,7
3
tRC(tCK)
MRSC
n/a
n/a
A9
A8
A7
A5
A4
0
1
0
1
0
1
0
1
0
0
1
1
4
4
6
8
3
5
must be met before any command can be issued. t
tRL(tCK)
n/a
n/a
A3
0
1
0
1
4
4
6
8
3
5
Non-multiplexed (Default)
Internal 50Ω
On-Die Termination
DLL reset
Drive Impedance
Address MUX
Off (Default)
External(ZQ)
Multiplexed
DLL enable
DLL Reset
tWL(tCK)
Burst Length(BL)
n/a
n/a
On
5
5
7
9
4
6
4
(Default)
2 (Default)
5
Reserved
6
(Default)
4
8
Valid Frequency Range
533-175
266-175
266-175
400-175
200-175
333-175
(MHz)
n/a
n/a
8
MRSC
is measured like
RC
is 4 cycles.
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