IS49NLC36160-25EBL ISSI, IS49NLC36160-25EBL Datasheet - Page 25

• Manufacturer Part Number: IS49NLC36160-25EBL
• Description: DRAM 576M, x36, 400Mhz RLDRAM2
• Manufacturer: ISSI

Specifications of IS49NLC36160-25EBL

• Rohs: yes
• Organization: 16 M x 36
• Package / Case: FBGA-144
• Memory Size: 576 Mbit
• Maximum Clock Frequency: 400 MHz
• Access Time: 2.5 ns
• Supply Voltage - Max: 2.63 V
• Supply Voltage - Min: 2.38 V
• Maximum Operating Current: 380 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT

IS49NLC96400,IS49NLC18320,IS49NLC36160
4 IEEE 1149.1 TAP and Boundary Scan
RLDRAM
instructions to test the interconnection between the memory I/Os and printed circuit board traces or other components. In
conformance with IEEE Standard 1149.1, the memory contains a TAP controller, instruction register, boundary scan register, bypass
register, and ID register. The TAP operates in accordance with IEEE Standard 1149.1-2001 (JTAG) with the exception of the ZQ pin. To
guarantee proper boundary-scan testing of the ZQ pin, MRS bit M8 needs to be set to 0 until the JTAG testing of the pin is complete.
Note that on power up, the default state of MRS bit M8 is logic LOW.
If the memory boundary scan register is to be used upon power up and prior to the initialization of the device, the CK and CK# pins
meet V
loaded, and subsequently cause unexpected results from address pins that are dependent upon the state of the mode register. If
these measures cannot be taken, the part must be initialized prior to boundary scan testing. If a full initialization is not practical or
feasible prior to boundary scan testing, a single MRS command with desired settings may be issued instead. After the single MRS
command is issued, the t
4.1 Disabling the JTAG feature
The RLDRAM
prevent clocking of the device. TDI and TMS are internally pulled up and may be left disconnected. They may alternately be
connected to V
which will not interfere with device operation.
4.2 Test Access Port Signal List:
Test Clock (TCK)
This signal uses V
of TCK. All outputs are driven from the falling edge of TCK.
Test Mode Select (TMS)
This signal uses V
edge of TCK.
Test Data-In (TDI)
This signal uses V
can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded
into the TAP instruction register. TDI is connected to the most significant bit (MSB) of any register. For more information regarding
instruction register loading, please see the TAP Controller State Diagram.
Test Data-Out (TDO)
This signal uses V
The TDO output driver is only active during the Shift-IR and Shift-DR TAP controller states. In all other states, the TDO pin is in a High-
Z state. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. For more
information, please see the TAP Controller State Diagram.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00F, 12/4/2012
ID
®
(DC) or CS# be held HIGH from power up until testing. Not doing so could result in inadvertent MRS commands to be
2 Memory devices have a serial boundary-scan test access port (TAP) that allow the use of a limited set of JTAG
®
2 Memory can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (V
DD
DD
DD
DDQ
DD
through a pull-up resistor. TDO should be left disconnected. On power-up, the device will come up in a reset state,
as a power supply. The test clock is used only with the TAP controller. All inputs are captured on the rising edge
as a power supply. The TMS input is used to send commands to the TAP controller and is sampled on the rising
as a power supply. The TDI input is used to serially input test instructions and information into the registers and
as a power supply. The TDO output ball is used to serially clock test instructions and data out from the registers.
MRSC
parameter must be satisfied prior to boundary scan testing.
25
SS
) to