IS49NLC36160-25EBL ISSI, IS49NLC36160-25EBL Datasheet - Page 3

• Manufacturer Part Number: IS49NLC36160-25EBL
• Description: DRAM 576M, x36, 400Mhz RLDRAM2
• Manufacturer: ISSI

Specifications of IS49NLC36160-25EBL

• Rohs: yes
• Organization: 16 M x 36
• Package / Case: FBGA-144
• Memory Size: 576 Mbit
• Maximum Clock Frequency: 400 MHz
• Access Time: 2.5 ns
• Supply Voltage - Max: 2.63 V
• Supply Voltage - Min: 2.38 V
• Maximum Operating Current: 380 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT

IS49NLC96400,IS49NLC18320,IS49NLC36160
1.2 576Mb (32Mx18) Common I/O BGA Ball-out (Top View)
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00F, 12/4/2012
M
CS#,WE#,REF# Command control pins
A
B
C
D
G
H
K
N
P
R
U
V
E
F
L
T
J
DNU,NF
Symbol
VDDQ
QVLD
VSSQ
VEXT
VREF
Total
VDD
DQ*
BA*
DK*
QK*
VSS
VTT
CK*
DM
ZQ
A*
T*
VREF
A22
A21
VREF
REF#
VDD
WE#
VDD
BA2
A18
A15
VTT
NF
VSS
VTT
A5
A8
DK
1
3
1
2
Description
Supply voltage
Ground
DQ power supply
DQ Ground
Supply voltage
Reference voltage
Termination voltage
Address - A0-22
Banks - BA0-2
I/O
Input data clock(Differential inputs)
Output data clocks(outputs)
Input clocks (CK, CK#)
Input data mask
External impedance (25–60Ω)
Data valid
Do not use, No function
JTAG - TCK,TMS,TDO,TDI
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
A16
QK1
VSS
NF
DK#
CS#
A6
A9
ZQ
2
3
4
4
4
4
4
4
4
4
4
DQ14
DQ15
DQ16
DQ17
QK1#
VEXT
VEXT
DQ4
DQ5
DQ6
DQ7
DQ8
VDD
VDD
A17
VSS
VSS
A7
3
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
4
5
6
Ball count
7
144
16
16
12
23
18
20
8
4
2
4
3
2
4
2
1
3
1
1
4
8
Notes:
NOTES:
NOTES:
1. Reserved for future use. This may optionally be
1) Reserved for future use. This may
1) Reserved for future use. This may
connected to GND.
optionally be connected to GND.
optionally be connected to GND.
2. Reserved for future use. This signal is internally
2) Reserved for future use. This signal is
2) Reserved for future use. This signal is
connected and has parasitic characteristics of an
address input signal. This may optionally be
internally connected and has parasitic
internally connected and has parasitic
connected to GND.
characteristics of an address input signal.
characteristics of an address input signal.
3. No function. This signal is internally connected and
This may optionally be connected to
This may optionally be connected to
has parasitic characteristics of a clock input signal.
GND.
GND.
This may optionally be connected to GND.
3) No function. This signal is internally
3) No function. This signal is internally
4. Do not use. This signal is internally connected and
connected and has parasitic
connected and has parasitic
has parasitic characteristics of a I/O. This may
optionally be connected to GND. Note that if ODT is
characteristics of a clock input signal.
characteristics of a clock input signal.
enabled, these pins are High-Z.
This may optionally be connected to
This may optionally be connected to
GND.
GND.
4) Do not use. This signal is internally
4) Do not use. This signal is internally
connected and has parasitic
connected and has parasitic
characteristics of a I/O. This may
characteristics of a I/O. This may
optionally be connected to GND. Note
optionally be connected to GND. Note
that if ODT is enabled, these pins will be
that if ODT is enabled, these pins will be
connected to VTT.
connected to VTT.
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
9
DQ10
DQ11
DQ12
DQ13
QK0#
VEXT
VEXT
DQ0
DQ1
DQ2
DQ3
VDD
VDD
DQ9
A12
VSS
VSS
A2
10
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
TMS
QK0
TDO
BA0
BA1
A14
A11
A1
A4
11
4
4
4
4
4
4
4
4
4
QVLD
VDD
VDD
A20
A13
A10
A19
TCK
VTT
VSS
CK#
DM
VSS
VTT
TDI
A0
A3
12
CK
3