AS4C8M16S-7BNTR Alliance Memory, AS4C8M16S-7BNTR Datasheet - Page 10

• Manufacturer Part Number: AS4C8M16S-7BNTR
• Description: DRAM 128Mb, 3.3V, 143Mhz 8M x 16 SDRAM
• Manufacturer: Alliance Memory

Specifications of AS4C8M16S-7BNTR

• Rohs: yes

precharge function should be issued m cycles after the clock edge in which the last data-in element is
registered, where m equals t
must be used to mask input data, starting with the clock edge following the last data-in element and
ending with the clock edge on which the BankPrecharge/PrechargeAll command is entered (refer to the
following figure).
FEBRUARY 2011
CLK
COMMAND
t
t
DQ
CLK
COMMAND
CAS# latency=2
CAS# latency=3
CK2,
CK3,
issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid
data contention, input data must be removed from the DQs at least one clock cycle before the first
read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
DQ
DQ
Figure 12. Write Interrupted by a Read
The Read command that interrupts a write burst without auto precharge function should be
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
Figure 11. Write Interrupted by a Write
T0
T0
NOP
NOP
WRITE A
WRITE A
T1
DIN A
T1
WR
DIN A
DIN A
/t
CK
0
0
0
rounded up to the next whole number. In addition, the DQM signals
WRITE B
READ B
T2
DIN B
T2
don’t care
don’t care
0
T3
T3
NOP
DIN B
NOP
don’t care
1
10
T4
T4
DOUT B
DIN B
NOP
NOP
(Burst Length = 4, CAS# Latency = 2, 3)
2
0
T5
T5
DOUT B
DIN B
NOP
NOP
Input data must be removed from the DQ
at least one clock cycle before the Read
data appears on the outputs to avoid data
contention
DOUT B
(Burst Length = 4)
3
0
T6
T6
1
DOUT B
NOP
NOP
DOUT B
1
T7
T7
DOUT B
NOP
NOP
2
DOUT B
2
T8
T8
DOUT B
NOP
NOP
AS4C8M16S
3
3