MAX195ACDE Maxim Integrated, MAX195ACDE Datasheet - Page 15
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MAX195ACDE
Manufacturer Part Number
MAX195ACDE
Description
Analog to Digital Converters - ADC
Manufacturer
Maxim Integrated
Datasheet
1.MAX195BEPE.pdf
(28 pages)
Specifications of MAX195ACDE
Number Of Channels
1
Architecture
SAR
Conversion Rate
85 KSPs
Resolution
16 bit
Input Type
Single-Ended
Interface Type
QSPI, Serial (SPI, Microwire)
Operating Supply Voltage
4.75 V to 5.25 V
Maximum Power Dissipation
842 mW
Number Of Converters
1
Voltage Reference
5 V
Digital noise can easily be coupled to AIN and REF. The
conversion clock (CLK) and other digital signals that are
active during input acquisition contribute noise to the con-
version result. If the noise signal is synchronous to the
sampling interval, an effective input offset is produced.
Asynchronous signals produce random noise on the input,
whose high-frequency components may be aliased into
the frequency band of interest. Minimize noise by present-
ing a low impedance (at the frequencies contained in the
noise signal) at the inputs. This requires bypassing AIN to
AGND, or buffering the input with an amplifier that has a
small-signal bandwidth of several megahertz, or prefer-
ably both. AIN has a bandwidth of about 16MHz.
Offsets resulting from synchronous noise (such as the
conversion clock) are canceled by the MAX195’s cali-
bration scheme. However, because the magnitude of
the offset produced by a synchronous signal depends
on the signal’s shape, recalibration may be appropriate
if the shape or relative timing of the clock or other digi-
tal signals change, as might occur if more than one
clock signal or frequency is used.
Avoid degrading dynamic performance by choosing an
amplifier with distortion much less than the MAX195’s
THD (-97dB, or 0.0014%) at frequencies of interest. If
the chosen amplifier has insufficient common-mode
rejection, which results in degraded THD performance,
use the inverting configuration (positive input ground-
ed) to eliminate errors from this source. Low tempera-
ture-coefficient, gain-setting resistors reduce linearity
errors caused by resistance changes due to self-heat-
Figure 15. AIN Buffer for AC/DC Use
IN
2
3
MAX427
+15V
-15V
16-Bit, 85ksps ADC with 10µA Shutdown
______________________________________________________________________________________
7
4
6
0.1 F
0.1 F
Digital Noise
100pF
1k
1k
Distortion
2
ELANTEC
EL2003
-15V
+15V
1
4
ing. Also, to reduce linearity errors due to finite amplifier
gain, use an amplifier circuit with sufficient loop gain at
the frequencies of interest (Figures 14, 15, 16).
If DC accuracy is important, choose a buffer with an
offset much less than the MAX195’s maximum offset
(±3LSB = ±366µV for a ±4V input range), or whose
offset can be trimmed while maintaining good stability
over the required temperature range.
Figure 14 shows a good circuit for DC and low-frequen-
cy use. The MAX400 has very low offset (10µV) and
drift (0.2µV/°C), and low voltage noise (10nV/ √ Hz) as
well. However, its gain-bandwidth product (GBW) is
much too low to drive AIN directly, so the analog input
is bypassed to present a low impedance at high fre-
quencies. The large bypass capacitor is isolated from
the amplifier output by a 100Ω resistor, which provides
additional noise filtering. Since the ±15V supplies
exceed the AIN range, add protection diodes at AIN
(see REF and AIN Input Protection section).
Figure 15 shows a wide-bandwidth amplifier (MAX427)
driving a wideband video buffer, which is capable of
driving AIN and a small bypass capacitor (for noise
reduction) directly. The video buffer is inside the
MAX427’s feedback loop, providing good DC accura-
cy, while the buffer’s low output impedance and high-
current capability provide good AC performance. AIN is
diode-clamped to the ±5V rails to prevent overvoltage.
The MAX427’s 15µV maximum offset voltage, 0.8µV/°C
maximum drift, and less than 5nV/ √ Hz noise specifica-
tions make this an excellent choice for AC/DC use.
7
0.1 F
0.1 F
0.0033 F
-5V
1N914
+5V
Recommended Circuits
1N914
10
DC Accuracy
AIN
15