S912XEG128J2MAL Freescale Semiconductor, S912XEG128J2MAL Datasheet - Page 138
S912XEG128J2MAL
Manufacturer Part Number
S912XEG128J2MAL
Description
16-bit Microcontrollers - MCU 16BIT 128K FLASH 16K RAM
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEG128J2MAL.pdf
(1324 pages)
Specifications of S912XEG128J2MAL
Rohs
yes
Core
RISC
Processor Series
HCS12X
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
128 KB
Data Ram Size
12 KB
On-chip Adc
Yes
Operating Supply Voltage
5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-112
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
8
Data Rom Size
4 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
On-chip Dac
Yes
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S912XEG128J2MAL
Manufacturer:
NXP/恩智浦
Quantity:
20 000
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1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.46
138
Address 0x0259
Write:Never, writes to this register have no effect.
Field
PTP
PTP
PTP
PTP
Reset
3
2
1
0
W
R
Port P general purpose input/output data—Data Register
Port P pin 3 is associated with the PWM output channel 3 and the SS signal of SPI1.
The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 3 is
enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
Port P general purpose input/output data—Data Register
Port P pin 2 is associated with the PWM output channel 2 and the SCK signal of SPI1.
The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 2 is
enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
Port P general purpose input/output data—Data Register
Port P pin 1 is associated with the PWM output channel 1 and the MOSI signal of SPI1.
The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 1 is
enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
Port P general purpose input/output data—Data Register
Port P pin 0 is associated with the PWM output channel 0 and the MISO signal of SPI1.
The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 0 is
enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
PTIP7
Port P Input Register (PTIP)
u
7
= Unimplemented or Reserved
PTIP6
Table 2-41. PTP Register Field Descriptions (continued)
u
6
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 2-44. Port P Input Register (PTIP)
PTIP5
u
5
PTIP4
u
4
Description
u = Unaffected by reset
PTIP3
3
u
PTIP2
u
2
Freescale Semiconductor
PTIP1
u
1
Access: User read
PTIP0
u
0
(1)
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