S9S12P32J0VFTR Freescale Semiconductor, S9S12P32J0VFTR Datasheet - Page 119
S9S12P32J0VFTR
Manufacturer Part Number
S9S12P32J0VFTR
Description
16-bit Microcontrollers - MCU 16 BIT 32K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12P64VQK.pdf
(566 pages)
Specifications of S9S12P32J0VFTR
Rohs
yes
Core
S12
Processor Series
MC9S12P
Data Bus Width
16 bit
Maximum Clock Frequency
16 MHz
Program Memory Size
32 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.15 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
QFN-48
Mounting Style
SMD/SMT
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3.5.1
The S12PMMC controls the address buses and the data buses that interface the bus masters (CPU12,
S12SBDM) with the rest of the system (master buses). In addition the MMC handles all CPU read data
bus swapping operations. All internal resources are connected to specific target buses (see
3.5.1.1
The arbitration scheme allows only one master to be connected to a target at any given time. The following
rules apply when prioritizing accesses from different masters to the same target bus:
3.5.2
The MMC does not generate any interrupts.
Freescale Semiconductor
•
•
CPU12 always has priority over BDM.
BDM has priority over CPU12 when its access is stalled for more than 128 cycles. In the later case
the CPU will be stalled after finishing the current operation and the BDM will gain access to the
bus.
Chip Bus Control
Interrupts
Master Bus Prioritization regarding Access Conflicts on Target Buses
P-Flash
DBG
S12P-Family Reference Manual, Rev. 1.13
D-Flash
Figure 3-12. S12I platform
MMC “Crossbar Switch”
resources
CPU
BDM
XBUS0
S12X0
SRAM
S12X1
Memory Map Control (S12PMMCV1)
Peripherals
BDM
IPBI
Figure
3-12).
119
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