C8051F961-A-GM Silicon Labs, C8051F961-A-GM Datasheet - Page 217
C8051F961-A-GM
Manufacturer Part Number
C8051F961-A-GM
Description
8-bit Microcontrollers - MCU 128KB, DC-DC, LCD AES, QFN40
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F961-A-GM
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
128 KB
Data Ram Size
8448 B
On-chip Adc
Yes
Operating Supply Voltage
2.5 V to 3.3 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFN-40
Mounting Style
SMD/SMT
Number Of Programmable I/os
34
Number Of Timers
4
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C8051F96x
SFRPGCN Bit
Interrupt
Logic
SFRPAGE
CIP-51
SFRNEXT
SFRLAST
Figure 16.1. SFR Page Stack
Automatic hardware preserving and restoring of the SFR Page on interrupts may be enabled or disabled
as desired using the SFR Automatic Page Control Enable Bit located in the SFR Page Control Register
(SFR0CN). This function defaults to “enabled” upon reset. In this way, the autoswitching function will be
enabled unless disabled in software.
A summary of the SFR locations (address and SFR page) are provided in Table 16.3 in the form of an SFR
memory map. Each memory location in the map has an SFR page row, denoting the page in which that
SFR resides. Certain SFRs are accessible from ALL SFR pages, and are denoted by the “(ALL PAGES)”
designation. For example, the Port I/O registers P0, P1, P2, and P3 all have the “(ALL PAGES)” designa-
tion, indicating these SFRs are accessible from all SFR pages regardless of the SFRPAGE register value.
Rev. 0.5
217
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