C8051F961-A-GM Silicon Labs, C8051F961-A-GM Datasheet - Page 325
C8051F961-A-GM
Manufacturer Part Number
C8051F961-A-GM
Description
8-bit Microcontrollers - MCU 128KB, DC-DC, LCD AES, QFN40
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F961-A-GM
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
128 KB
Data Ram Size
8448 B
On-chip Adc
Yes
Operating Supply Voltage
2.5 V to 3.3 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFN-40
Mounting Style
SMD/SMT
Number Of Programmable I/os
34
Number Of Timers
4
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SFR Definition 25.5. PC0DCH: PC0 Debounce Configuration High
SFR Address = 0xFA; SFR Page = 0x2
Name
Reset
Bit
7:0
Type
Bit
PC0DCH[7:0]
7
0
Name
6
0
Pulse Counter Debounce High
Number of cumulative good samples seen by the integrator before recogniz-
ing the input as high. Sampling a low will decrement the count while sam-
pling a high will increment the count. The actual value used is PC0DCH plus
one. Switch bounce produces a random looking signal. The worst case
would be to bounce low at each sample point and not start incrementing the
integrator until the switch bounce settled. Therefore, minimum pulse width
should account for twice the debounce time. For example, using a sample
rate of 250 µs and a PC0DCH value of 0x13 will look for 20 cumulative
highs before recognizing the input as high (250 µs x (16+3+1) = 5 ms).
5
0
Rev. 0.5
PC0DCH[7:0]
4
0
R/W
3
0
Function
2
1
C8051F96x
1
0
0
0
325
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