C8051F961-A-GM Silicon Labs, C8051F961-A-GM Datasheet - Page 6
C8051F961-A-GM
Manufacturer Part Number
C8051F961-A-GM
Description
8-bit Microcontrollers - MCU 128KB, DC-DC, LCD AES, QFN40
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F961-A-GM
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
128 KB
Data Ram Size
8448 B
On-chip Adc
Yes
Operating Supply Voltage
2.5 V to 3.3 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFN-40
Mounting Style
SMD/SMT
Number Of Programmable I/os
34
Number Of Timers
4
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C8051F96x
15. Encoder/Decoder ................................................................................................. 207
16. Special Function Registers................................................................................. 216
17. Interrupt Handler.................................................................................................. 232
18. Flash Memory....................................................................................................... 244
19. Power Management ............................................................................................. 257
20. On-Chip DC-DC Buck Converter (DC0).............................................................. 269
6
15.1. Manchester Encoding.................................................................................... 208
15.2. Manchester Decoding.................................................................................... 209
15.3. Three-out-of-Six Encoding............................................................................ 210
15.4. Three-out-of-Six Decoding ............................................................................ 211
15.5. Encoding/Decoding with SFR Access ........................................................... 212
15.6. Decoder Error Interrupt.................................................................................. 212
15.7. Using the ENC0 module with the DMA.......................................................... 213
16.1. SFR Paging ................................................................................................... 216
16.2. Interrupts and SFR Paging ............................................................................ 216
17.1. Enabling Interrupt Sources ............................................................................ 232
17.2. MCU Interrupt Sources and Vectors.............................................................. 232
17.3. Interrupt Priorities .......................................................................................... 233
17.4. Interrupt Latency............................................................................................ 233
17.5. Interrupt Register Descriptions ...................................................................... 235
17.6. External Interrupts INT0 and INT1................................................................. 242
18.1. Programming the Flash Memory ................................................................... 244
18.2. Non-volatile Data Storage ............................................................................. 247
18.3. Security Options ............................................................................................ 247
18.4. Determining the Device Part Number at Run Time ....................................... 249
18.5. Flash Write and Erase Guidelines ................................................................. 250
18.6. Minimizing Flash Read Current ..................................................................... 252
19.1. Normal Mode ................................................................................................. 258
19.2. Idle Mode....................................................................................................... 258
19.3. Stop Mode ..................................................................................................... 259
19.4. Low Power Idle Mode .................................................................................... 259
19.5. Suspend Mode .............................................................................................. 263
19.6. Sleep Mode ................................................................................................... 263
19.7. Configuring Wakeup Sources........................................................................ 264
19.8. Determining the Event that Caused the Last Wakeup................................... 264
19.9. Power Management Specifications ............................................................... 268
20.1. Startup Behavior............................................................................................ 270
20.4. Optimizing Board Layout ............................................................................... 271
18.1.1. Flash Lock and Key Functions .............................................................. 244
18.1.2. Flash Erase Procedure ......................................................................... 244
18.1.3. Flash Write Procedure .......................................................................... 245
18.1.4. Flash Write Optimization ....................................................................... 246
18.5.1. VDD Maintenance and the VDD Monitor .............................................. 250
18.5.2. PSWE Maintenance .............................................................................. 251
18.5.3. System Clock ........................................................................................ 251
Rev. 0.5
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