C8051F964-A-GQ Silicon Labs, C8051F964-A-GQ Datasheet - Page 88
C8051F964-A-GQ
Manufacturer Part Number
C8051F964-A-GQ
Description
8-bit Microcontrollers - MCU 64KB DC-DC LCD AES
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F964-A-GQ
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
24.5 MHz
Program Memory Size
64 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.8 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFP-80
Mounting Style
SMD/SMT
Available stocks
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Part Number:
C8051F964-A-GQ
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Silicon Laboratories Inc
Quantity:
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C8051F96x
SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration
SFR Page = 0x0; SFR Address = 0xBA
88
Name AD012BE
Reset
Type
Bit
Bit
5:3
2:0
7
6
AD0SJST[2:0] ADC0 Accumulator Shift and Justify.
AD0RPT[2:0] ADC0 Repeat Count.
AD012BE
R/W
AD0AE
Name
7
0
AD0AE
ADC0 12-Bit Mode Enable.
Enables 12-bit Mode.
0: 12-bit Mode Disabled.
1: 12-bit Mode Enabled.
ADC0 Accumulate Enable.
Enables multiple conversions to be accumulated when burst mode is disabled.
0: ADC0H:ADC0L contain the result of the latest conversion when Burst Mode is
disabled.
1: ADC0H:ADC0L contain the accumulated conversion results when Burst Mode
is disabled. Software must write 0x0000 to ADC0H:ADC0L to clear the accumu-
lated result.
This bit is write-only. Always reads 0b.
Specifies the format of data read from ADC0H:ADC0L.
000: Right justified. No shifting applied.
001: Right justified. Shifted right by 1 bit.
010: Right justified. Shifted right by 2 bits.
011: Right justified. Shifted right by 3 bits.
100: Left justified. No shifting applied.
All remaining bit combinations are reserved.
Selects the number of conversions to perform and accumulate in Burst Mode.
This bit field must be set to 000 if Burst Mode is disabled.
000: Perform and Accumulate 1 conversion.
001: Perform and Accumulate 4 conversions.
010: Perform and Accumulate 8 conversions.
011: Perform and Accumulate 16 conversions.
100: Perform and Accumulate 32 conversions.
101: Perform and Accumulate 64 conversions.
All remaining bit combinations are reserved.
W
6
0
5
0
AD0SJST[2:0]
R/W
Rev. 0.5
4
0
Function
3
0
2
0
AD0RPT[2:0]
R/W
1
0
0
0
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