SiM3C167-B-GM Silicon Labs, SiM3C167-B-GM Datasheet
SiM3C167-B-GM
Specifications of SiM3C167-B-GM
Related parts for SiM3C167-B-GM
SiM3C167-B-GM Summary of contents
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ARM® Cortex™-M3 CPU - 80 MHz maximum frequency - Single-cycle multiplication, hardware division support - Nested vectored interrupt control (NVIC) with 16 priority levels Memory - 32–256 kB Flash, in-system programmable - 8–32 kB SRAM (including 4 kB retention ...
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SiM3C1xx Ta ble of Contents 1. Related Documents and Conventions ...............................................................................4 1.1. Related Documents........................................................................................................4 1.1.1. SiM3U1xx/SiM3C1xx Reference Manual...............................................................4 1.1.2. Hardware Access Layer (HAL) API Description ....................................................4 1.1.3. ARM Cortex-M3 Reference Manual.......................................................................4 1.2. Conventions ...................................................................................................................4 2. Typical Connection Diagrams ............................................................................................5 2.1. ...
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I2C (I2C0, I2C1)................................................................................................... 43 4.6.6. I2S (I2S0)............................................................................................................. 44 4.7. Analog .......................................................................................................................... 45 4.7.1. 12-Bit Analog-to-Digital Converters (SARADC0, SARADC1).............................. 45 4.7.2. Sample Sync Generator (SSG0) ......................................................................... 45 4.7.3. 10-Bit Digital-to-Analog Converter (IDAC0, IDAC1) ............................................ 45 4.7.4. 16-Channel Capacitance-to-Digital Converter (CAPSENSE0) ...
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SiM3C1xx 1. Related Documents and Conventions 1.1. Related Documents This data sheet accompanies several documents to provide the complete description of the SiM3C1xx device family. 1.1.1. SiM3U1xx/SiM3C1xx Reference Manual The Silicon Laboratories SiM3U1xx/SiM3C1xx Reference Manual provides detailed functional descriptions for ...
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Typical Connection Diagrams This section provides typical connection diagrams for SiM3C1xx devices. 2.1. Power Figure 2.1 shows a typical connection diagram for the power pins of the SiM3C1xx devices when the internal regulator is in use (in) ...
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SiM3C1xx 3. Electrical Specifications 3.1. Electrical Characteristics All electrical parameters in all tables are specified under the conditions listed in Table 3.1, unless stated otherwise. Table 3.1. Recommended Operating Conditions Parameter Operating Supply Voltage on VDD Operating Supply Voltage on ...
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Table 3.2. Power Consumption Parameter Digital Core Supply Current 2,3,4,5 Normal Mode —Full speed with code executing from Flash, peripheral clocks ON 2,3,4,5 Normal Mode —Full speed with code executing from Flash, peripheral clocks OFF 2,3,4,6 Power Mode 1 —Full ...
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SiM3C1xx Table 3.2. Power Consumption (Continued) Parameter 2,3 Power Mode 9 —Low Power Shutdown with VREG0 disabled, powered through VDD and VIO 2,3 Power Mode 9 —Low Power Shutdown with VREG0 in low- power mode, VDD and VIO pow- ered ...
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Table 3.2. Power Consumption (Continued) Parameter Analog Peripheral Supply Currents Voltage Regulator (VREG0) Voltage Regulator (VREG0) Sense I External Regulator (EXTVREG0) PLL0 Oscillator (PLL0OSC) Low-Power Oscillator (LPOSC0) Low-Frequency Oscillator (LFOSC0) Notes: 1. Perhipheral currents drop to zero when peripheral clock ...
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SiM3C1xx Table 3.2. Power Consumption (Continued) Parameter 8 External Oscillator (EXTOSC0) SARADC0, SARADC1 Temperature Sensor Internal SAR Reference VREF0 Comparator 0 (CMP0), Comparator 1 (CMP1) Capacitive Sensing (CAPSENSE0) 7 IDAC0 , 7 IDAC1 7 IVC0 Voltage Supply Monitor (VMON0) Notes: ...
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Table 3.2. Power Consumption (Continued) Parameter Flash Current on VDD Write Operation Erase Operation Notes: 1. Perhipheral currents drop to zero when peripheral clock and peripheral are disabled, unless otherwise noted. 2. Currents are additive. For example, where functions increases ...
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SiM3C1xx Table 3.4. Reset and Supply Monitor Parameter V High Supply Monitor Threshold DD (VDDHITHEN = 1) V Low Supply Monitor Threshold DD (VDDHITHEN = 0) V Supply Monitor Threshold REGIN Power-On Reset (POR) Threshold V Ramp Time DD Reset ...
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Table 3.5. On-Chip Regulators Parameter 3.3 V Regulator Characteristics (VREG0, Supplied from VREGIN Pin) Output Voltage (at VDD pin) Output Current (at VDD pin)* Output Load Regulation Output Capacitance *Note: Total current VREG0 is capable of providing. Any current consumed ...
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SiM3C1xx Table 3.6. External Regulator Parameter Symbol Input Voltage Range (at V REGIN VREGIN) Output Voltage (at V EXREGOUT EXREGOUT) NPN Current Drive I NPN PNP Current Drive I PNP EXREGBD Voltage (PNP V EXREGBD Mode) Standalone Mode Output I ...
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Table 3.7. Flash Memory Parameter 1 Write Time 1 Erase Time V Voltage During Programming DD Endurance (Write/Erase Cycles) 2 Retention Notes: 1. Does not include sequencing time before and after the write/erase operation, which may take ...
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SiM3C1xx Table 3.8. Internal Oscillators (Continued) Parameter Low Power Oscillator (LPOSC0) Oscillator Frequency Divided Oscillator Frequency Power Supply Sensitivity Temperature Sensitivity Low Frequency Oscillator (LFOSC0) Oscillator Frequency Power Supply Sensitivity Temperature Sensitivity RTC0 Oscillator (RTC0OSC) Missing Clock Detector Trigger Frequency ...
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Table 3.10. SAR ADC Parameter Resolution Supply Voltage Requirements (VDD) Throughput Rate (High Speed Mode) Throughput Rate (Low Power Mode) Tracking Time SAR Clock Frequency Conversion Time Sample/Hold Capacitor Input Pin Capacitance Input Mux Impedance Voltage Reference Range 1 Input ...
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SiM3C1xx Table 3.10. SAR ADC (Continued) Parameter Differential Nonlinearity (Guaranteed Monotonic) Offset Error (using VREFGND) Offset Temperatue Coefficient 3 Slope Error Dynamic Performance with 10 kHz Sine Wave Input 1 dB below full scale, Max throughput Signal-to-Noise Signal-to-Noise Plus ...
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Table 3.11. IDAC Parameter Static Performance Resolution Integral Nonlinearity Differential Nonlinearity (Guaranteed Monotonic) Output Compliance Range Full Scale Output Current Offset Error Full Scale Error Tempco VDD Power Supply Rejection Ratio Test Load Impedance ( Dynamic Performance ...
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SiM3C1xx Table 3.12. Capacitive Sense Parameter Single Conversion Time (Default Configuration) Maximum External Capacitive Load Maximum External Series Impedance Table 3.13. Current-to-Voltage Converter (IVC) Parameter Supply Voltage (VDD) Input Pin Voltage Minimum Input Current (source) Integral Nonlinearity Full Scale ...
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Table 3.14. Voltage Reference Electrical Characteristics – 1 +85 °C unless otherwise specified. DD Parameter Internal Fast Settling Reference Output Voltage Temperature Coefficient Turn-on Time Power Supply Rejection PSRR On-Chip Precision Reference (VREF0) ...
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SiM3C1xx Table 3.15. Temperature Sensor Parameter Offset Offset Error* Slope Slope Error* Linearity Turn-on Time *Note: Represents one standard deviation from the mean. 22 Symbol Test Condition °C OFF °C OFF ...
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Table 3.16. Comparator Parameter Response Time, CMPMD = 00 (Highest Speed) Response Time, CMPMD = 11 (Lowest Power) Positive Hysteresis Mode 0 (CPMD = 00) Negative Hysteresis Mode 0 (CPMD = 00) Positive Hysteresis Mode 1 (CPMD = 01) Negative ...
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SiM3C1xx Table 3.16. Comparator (Continued) Parameter Positive Hysteresis Mode 3 (CPMD = 11) Negative Hysteresis Mode 3 (CPMD = 11) Input Range (CP+ or CP–) Input Pin Capacitance Common-Mode Rejection Ratio Power Supply Rejection Ratio Input Offset Voltage Input Offset ...
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Table 3.17. Port I/O Parameter Standard I/O (PB0, PB1, and PB2 Tolerant I/O (PB3), and RESET Output High Voltage* Output Low Voltage* Input High Voltage Input Low Voltage Pin Capacitance Weak Pull-Up Current (Input Voltage = 0 V) ...
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SiM3C1xx Table 3.17. Port I/O (Continued) Parameter Output Fall Time Input High Voltage Input Low Voltage N-Channel Sink Current Limit (2.7 V < V < IOHD See Figure 3.1 Total N-Channel Sink Current ...
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Table 3.17. Port I/O (Continued) Parameter P-Channel Source Current Limit (2.7 V < VIOHD < VIOHD – 0 See Figure 3.2 Total P-Channel Source Current on P4.0-P4.5 (DC) Pin Capacitance Weak Pull-Up Current in ...
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SiM3C1xx 350 300 250 200 150 S afe O p eratin 100 Figure 3.1. Maximum Sink Current vs. PB4.x Pin Voltage 250 200 150 100 Figure 3.2. Maximum ...
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Thermal Conditions Table 3.18. Thermal Conditions Parameter Thermal Resistance* *Note: Thermal resistance assumes a multi-layer PCB with any exposed pad soldered to a PCB pad. 3.3. Absolute Maximum Ratings Stresses above those listed under Table 3.19 may cause permanent ...
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SiM3C1xx Table 3.19. Absolute Maximum Ratings (Continued) Parameter Voltage on I/O pins, Port Bank 3 I/O Total Current Sunk into Supply Pins Total Current Sourced out of Ground Pins Current Sourced or Sunk by Any I/O Pin Current Injected on ...
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Table 3.19. Absolute Maximum Ratings (Continued) Parameter Power Dissipation °C A *Note: VSS and VSSHD provide separate return current paths for device supplies, but are not isolated. They must always be connected to the same potential ...
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SiM3C1xx 4. Precision32™ SiM3C1xx System Overview The SiM3C1xx Precision32™ devices are fully integrated, mixed-signal system-on-a-chip MCUs. Highlighted features are listed below. Refer to Table 5.1 for specific product feature selection and part ordering numbers. Core: 32-bit ARM Cortex-M3 CPU. ...
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User firmware has complete control of all peripherals and may individually shut down and gate the clocks of any or all peripherals for power savings. The on-chip debugging interface (SWJ-DP) ...
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SiM3C1xx 4.1. Power 4.1.1. LDO and Voltage Regulator (VREG0) The SiM3C1xx devices include two internal regulators: the core LDO Regulator and the Voltage Regulator (VREG0). The LDO Regulator converts a 1.8–3.6 V supply to the core operating voltage of 1.8 ...
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Device Power Modes The SiM3C1xx devices feature four low power modes in addition to normal operating mode. Several peripherals provide wake up sources for these low power modes, including the Low-Power Timer (LPT0), RTC0 (alarms and oscillator failure notification), ...
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SiM3C1xx 4.2. I/O 4.2.1. General Features The SiM3C1xx ports have the following features: Push-pull or open-drain output modes and analog or digital modes. Option for high or low output drive strength. Port Match allows the device to ...
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Clocking The SiM3C1xx devices have two system clocks: AHB and APB. The AHB clock services memory peripherals and is derived from one of seven sources: the RTC0 timer clock (RTC0TCLK), the Low Frequency Oscillator, the Low Power Oscillator, the ...
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SiM3C1xx 4.3.1. PLL (PLL0) The PLL module consists of a dedicated Digitally-Controlled Oscillator (DCO) that can be used in Free-Running mode without a reference frequency, Frequency-Locked to a reference frequency, or Phase-Locked to a reference frequency. The reference frequency for ...
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Data Peripherals 4.4.1. 16-Channel DMA Controller The DMA facilitates autonomous peripheral operation, allowing the core to finish tasks more quickly without spending time polling or waiting for peripherals to interrupt. This helps reduce the overall power consumption of the ...
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SiM3C1xx 4.5. Counters/Timers and PWM 4.5.1. Programmable Counter Array (EPCA0, PCA0, PCA1) The SiM3C1xx devices include two types of PCA module: Enhanced and Standard. The Enhanced Programmable Counter Array (EPCA0) and Standard Programmable Counter Array (PCA0, PCA1) modules are timer/counter ...
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Real-Time Clock (RTC0) The RTC0 module includes a 32-bit timer that allows hours of independent time-keeping when used with a 32.768 kHz watch crystal. The RTC0 provides three alarm events in addition to a missing clock ...
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SiM3C1xx 4.6. Communications Peripherals 4.6.1. External Memory Interface (EMIF0) The External Memory Interface (EMIF0) allows external parallel asynchronous devices, like SRAMs and LCD controllers, to appear as part of the system memory map. The EMIF0 module includes the following features: ...
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Internal transmit and receive FIFOs with flush capability and support for byte, half-word, and word reads and writes. Data bit lengths from bits. Programmable inter-packet transmit delays. Auto-baud detection with support for the ...
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SiM3C1xx Spike suppression times the APB period. 2 4.6. (I2S0) 2 The I S module receives digital data from an external source over a data line in the standard I justified, or time domain ...
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Analog 4.7.1. 12-Bit Analog-to-Digital Converters (SARADC0, SARADC1) The SARADC0 and SARADC1 modules on SiM3C1xx devices are Successive Approximation Register (SAR) Analog to Digital Converters (ADCs). The key features of the SARADC module are: Single-ended 12-bit and 10-bit modes. ...
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SiM3C1xx 4.7.4. 16-Channel Capacitance-to-Digital Converter (CAPSENSE0) The Capacitance Sensing module measures capacitance on external pins and converts digital value. The CAPSENSE module has the following features: Multiple start-of-conversion sources (CSnTx). Option to convert to 12, ...
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Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: The core halts program execution. Module registers are initialized to their defined ...
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SiM3C1xx 4.9. Security The peripherals on the SiM3C1xx devices have a register lock and key mechanism that prevents any undesired accesses of the peripherals from firmware. Each bit in the PERIPHLOCKx registers controls a set of peripherals. A key sequence ...
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... Ordering Information – B Family – U (USB), C (Core) Core – M3 (Cortex M3) Silicon Labs Figure 5.1. SiM3C1xx Part Numbering All devices in the SiM3C1xx family have the following features: Core: ARM Cortex-M3 with maximum operating frequency of 80 MHz. Flash Program Memory: 32-256 kB, in-system programmable. ...
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... SiM3C1xx SiM3C167-B-GM 256 32 SiM3C167-B-GQ 256 32 SiM3C166-B-GM 256 32 SiM3C166-B-GQ 256 32 SiM3C164-B-GM 256 32 SiM3C157-B-GM 128 32 SiM3C157-B-GQ 128 32 SiM3C156-B-GM 128 32 SiM3C156-B-GQ 128 32 SiM3C154-B-GM 128 32 SiM3C146-B- SiM3C146-B- SiM3C144-B- SiM3C136-B- ...
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Pin Definitions and Packaging Information 6.1. SiM3C1x7 Pin Definitions PB4.5 1 PB4.4 2 PB4.3 3 VSSHD 4 VIOHD 5 PB4.2 6 PB4.1 7 PB4.0 8 PB3.11 9 PB3.10 10 PB3.9 11 PB3.8 12 PB3.7 13 PB3.6 14 PB3.5 15 ...
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SiM3C1xx D1 A48 A47 PB4 B36 PB4.4 A2 PB4 VIOHD B2 VSSHD A4 PB4.2 B3 PB3.11 A5 PB4.1 B4 PB3.10 A6 PB4.0 B5 PB3.9 A7 PB3.8 B6 PB3.7 A8 PB3.6 B7 PB3.5 A9 PB3.4 B8 PB3.3 ...
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Table 6.1. Pin Definitions and alternate functions for SiM3C1x7 Pin Name Type VSS Ground VDD Power (Core) VIO Power (I/O) VREGIN Power (Regulator) VSSHD Ground (High Drive) VIOHD Power (High Drive) RESET Active-low Reset SWCLK/TCK Serial Wire/JTAG SWDIO/TMS Serial Wire/JTAG ...
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SiM3C1xx Table 6.1. Pin Definitions and alternate functions for SiM3C1x7 (Continued) Pin Name Type PB0.8 Standard I/O PB0.9 Standard I/O PB0.10 Standard I/O PB0.11 Standard I/O PB0.12 Standard I/O PB0.13 Standard I/O PB0.14 Standard I/O PB0.15 Standard I/O PB1.0 Standard ...
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Table 6.1. Pin Definitions and alternate functions for SiM3C1x7 (Continued) Pin Name Type PB1.9/ Standard I/O /ETM TRACECLK PB1.10 Standard I/O PB1.11 Standard I/O PB1.12 Standard I/O PB1.13 Standard I/O PB1.14 Standard I/O PB1.15 Standard I/O PB2.0 Standard I/O PB2.1 ...
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SiM3C1xx Table 6.1. Pin Definitions and alternate functions for SiM3C1x7 (Continued) Pin Name Type PB2.6 Standard I/O PB2.7 Standard I/O PB2.8 Standard I/O PB2.9 Standard I/O PB2.10 Standard I/O PB2.11 Standard I/O PB2.12 Standard I/O PB2.13 Standard I/O PB2.14 Standard ...
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Table 6.1. Pin Definitions and alternate functions for SiM3C1x7 (Continued) Pin Name Type PB3 Tolerant I/O PB3 Tolerant I/O PB3 Tolerant I/O PB3 Tolerant I/O PB3 Tolerant I/O PB3.9 5 ...
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SiM3C1xx Table 6.1. Pin Definitions and alternate functions for SiM3C1x7 (Continued) Pin Name Type PB4.0 High Drive I/O PB4.1 High Drive I/O PB4.2 High Drive I/O PB4.3 High Drive I/O PB4.4 High Drive I/O PB4.5 High Drive I/O Note: All ...
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SiM3C1x6 Pin Definitions PB4.3 1 VSSHD 2 VIOHD 3 PB4.2 4 PB4.1 5 PB4.0 6 PB3.9 7 PB3.8 8 PB3.7 9 PB3.6 10 PB3.5 11 PB3.4 12 PB3.3 13 PB3.2 14 PB3.1 15 PB3 Pin TQFP Figure ...
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SiM3C1xx PB4.3 1 VSSHD 2 VIOHD 3 PB4.2 4 PB4.1 5 PB4.0 6 PB3.9 7 PB3.8 8 PB3.7 9 PB3.6 10 PB3.5 11 PB3.4 12 PB3.3 13 PB3.2 14 PB3.1 15 PB3 pin QFN (TopView) VSS Figure ...
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Table 6.2. Pin Definitions and alternate functions for SiM3C1x6 Pin Name Type VSS Ground VDD Power (Core) VIO Power (I/O) VREGIN Power (Regulator) VSSHD Ground (High Drive) VIOHD Power (High Drive) RESET Active-low Reset SWCLK/TCK Serial Wire / JTAG SWDIO/TMS ...
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SiM3C1xx Table 6.2. Pin Definitions and alternate functions for SiM3C1x6 (Continued) Pin Name Type PB0.7 Standard I/O PB0.8 Standard I/O PB0.9 Standard I/O PB0.10 Standard I/O PB0.11 Standard I/O PB0.12 Standard I/O PB0.13 Standard I/O PB0.14/TDO/ Standard I/O / JTAG ...
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Table 6.2. Pin Definitions and alternate functions for SiM3C1x6 (Continued) Pin Name Type PB1.8 Standard I/O PB1.9 Standard I/O PB1.10 Standard I/O PB1.11 Standard I/O PB1.12 Standard I/O PB1.13 Standard I/O PB1.14 Standard I/O PB1.15 Standard I/O PB2.0 Standard I/O ...
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SiM3C1xx Table 6.2. Pin Definitions and alternate functions for SiM3C1x6 (Continued) Pin Name Type PB3 Tolerant I/O PB3 Tolerant I/O PB3 Tolerant I/O PB3 Tolerant I/O PB3 Tolerant I/O PB3.7 ...
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Table 6.2. Pin Definitions and alternate functions for SiM3C1x6 (Continued) Pin Name Type PB3 Tolerant I/O PB4.0 High Drive I/O PB4.1 High Drive I/O PB4.2 High Drive I/O PB4.3 High Drive I/O 7 XBR1 BE0 6 LSO0 ...
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SiM3C1xx 6.3. SiM3C1x4 Pin Definitions PB4.3 1 VSSHD 2 VIOHD 3 PB4.2 4 PB4.1 5 PB4.0 6 PB3.3 7 PB3.2 8 PB3.1 9 PB3 pin QFN (Top View) VSS Figure 6.5. SiM3C1x4-GM Pinout Rev.1.0 PB0 ...
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Table 6.3. Pin Definitions and Alternate Functions for SiM3C1x4 Pin Name Type VSS Ground VDD Power (Core) VIO Power (I/O) VREGIN Power (Regulator) VSSHD Ground (High Drive) VIOHD Power (High Drive) RESET Active-low Reset SWCLK Serial Wire SWDIO Serial Wire ...
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SiM3C1xx Table 6.3. Pin Definitions and Alternate Functions for SiM3C1x4 (Continued) Pin Name Type PB0.8 Standard I/O PB0.9 Standard I/O PB0.10 Standard I/O PB0.11 Standard I/O PB0.12 Standard I/O PB0.13 Standard I/O PB0.14 Standard I/O PB0.15 Standard I/O PB1.0 Standard ...
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Table 6.3. Pin Definitions and Alternate Functions for SiM3C1x4 (Continued) Pin Name Type PB3 Tolerant I/O PB3 Tolerant I/O PB3 Tolerant I/O PB4.0 High Drive I/O PB4.1 High Drive I/O PB4.2 High Drive I/O ...
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SiM3C1xx 6.4. LGA-92 Package Specifications Figure 6.6. LGA-92 Package Drawing Table 6.4. LGA-92 Package Dimensions Dimension aaa bbb ccc ddd eee Notes: 1. All dimensions shown are in millimeters (mm) ...
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Figure 6.7. LGA-92 Landing Diagram Table 6.5. LGA-92 Landing Diagram Dimensions Dimension Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. All feature sizes shown are at Maximum Material ...
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SiM3C1xx 6.4.1. LGA-92 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad µm minimum, all the way around the pad. 6.4.2. LGA-92 Stencil ...
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TQFP-80 Package Specifications Figure 6.8. TQFP-80 Package Drawing Table 6.6. TQFP-80 Package Dimensions Dimension Min Nominal Max — — 1.20 0.05 — 0.15 0.95 1.00 1.05 0.17 0.20 0.27 ...
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SiM3C1xx Table 6.6. TQFP-80 Package Dimensions (Continued) Dimension L L1 aaa bbb ccc ddd eee Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This package outline conforms ...
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Figure 6.9. TQFP-80 Landing Diagram Table 6.7. TQFP-80 Landing Diagram Dimensions Dimension C1 13.30 C2 13. Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on ...
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SiM3C1xx 6.5.1. TQFP-80 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad µm minimum, all the way around the pad. 6.5.2. TQFP-80 Stencil ...
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QFN-64 Package Specifications Figure 6.10. QFN-64 Package Drawing Table 6.8. QFN-64 Package Dimensions Dimension aaa bbb ccc ddd eee Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise ...
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SiM3C1xx Figure 6.11. QFN-64 Landing Diagram Table 6.9. QFN-64 Landing Diagram Dimensions Dimension Notes: 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at ...
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QFN-64 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad µm minimum, all the way around the pad. 6.6.2. QFN-64 Stencil Design ...
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SiM3C1xx 6.7. TQFP-64 Package Specifications Figure 6.12. TQFP-64 Package Drawing Table 6.10. TQFP-64 Package Dimensions Dimension 80 Min Nominal Max — — 1.20 0.05 — 0.15 0.95 1.00 ...
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Table 6.10. TQFP-64 Package Dimensions (Continued) Dimension Min aaa — bbb — ccc — ddd — Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This package outline conforms ...
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SiM3C1xx Figure 6.13. TQFP-64 Landing Diagram Table 6.11. TQFP-64 Landing Diagram Dimensions Dimension Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on the ...
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TQFP-64 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad µm minimum, all the way around the pad. 6.7.2. TQFP-64 Stencil Design ...
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SiM3C1xx 6.8. QFN-40 Package Specifications Figure 6.14. QFN-40 Package Drawing Table 6.12. QFN-40 Package Dimensions Dimension aaa bbb ccc ddd eee Notes: 1. All dimensions shown are in millimeters (mm) unless ...
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Figure 6.15. QFN-40 Landing Diagram Table 6.13. QFN-40 Landing Diagram Dimensions Dimension Notes: 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. ...
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SiM3C1xx 6.8.1. QFN-40 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad µm minimum, all the way around the pad. 6.8.2. QFN-40 Stencil ...
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... In addition, firmware can determine the revision of the device by checking the DEVICEID registers. Figure 7.1. LGA-92 SiM3C1x7 Revision Information Figure 7.2. TQFP-80 SiM3C1x7 Revision Information SiM3C167 B-GM 1131BCS701 KR e4 These characters identify the device revision SiM3C167 B-GQ 1131BCS701 TW e3 These characters identify the device revision Rev.1.0 SiM3C1xx 87 ...
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SiM3C1xx QFN-64 SiM3C166 1142BCS701 e3 Figure 7.3. SiM3C1x6 Revision Information Figure 7.4. SiM3C1x4 Revision Information 7.2. Comparator Rising/Falling Edge Flags in Debug Mode (CMP0, CMP1) 7.2.1. Problem On Revision A and Revision B devices, if the comparator output is high, ...
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OCUMENT HANGE IST Revision 0.8 to Revision 1.0 Added block diagram to front page; updated feature bullet lists. Electrical Specifications Tables Additions: Voltage Regulator Current Sense Supply Current, Typ = 3 µA (Table 3.2) ...
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... Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog- intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. ...