MAX1323ECM-T Maxim Integrated, MAX1323ECM-T Datasheet - Page 12

• Manufacturer Part Number: MAX1323ECM-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
The parallel digital interface outputs the 14-bit conver-
sion result. The interface includes the following control
signals: chip select (CS), read (RD), end of conversion
(EOC), end of last conversion (EOLC), convert start
(CONVST), shutdown (SHDN), all on (ALLON), internal
clock select (INTCLK /EXTCLK), and external clock
input (CLK). Figures 3 and 4, Table 1, and the Timing
Characteristics table show the operation of the inter-
Figure 3. Reading a Conversion—Internal Clock
Table 1. Reference Bypass Capacitors
NA = Not applicable (connect MSV directly to AGND).
12
MSV Bypass Capacitor to AGND
REF
REF Bypass Capacitor to AGND
REF+ Bypass Capacitor to AGND
REF+ to REF- Capacitor
REF- Bypass Capacitor to AGND
COM Bypass Capacitor to AGND
MS
______________________________________________________________________________________
Bypass Capacitor to AGND
CONVST
D0–D13
EOC
RD
LOCATION
Applications Information
TRACK
t
ACQ
SAMPLE
Digital Interface
UNIPOLAR (µF)
t
EOC1
2.2 || 0.1
2.2 || 0.1
2.2 || 0.1
0.01
0.01
0.1
0.1
face. The parallel interface goes high impedance when
RD = 1 or CS = 1.
To start a conversion using internal clock mode, pull
CONVST low for at least the acquisition time (t
T/H acquires the signal while CONVST is low, and con-
version begins on the rising edge of CONVST. The end-
of-conversion signal (EOC) or the end-of-last-conversion
signal (EOLC) pulses low when the conversion result is
available (Figure 3).
INPUT VOLTAGE RANGE
t
13
t
10
t
11
HOLD
t
12
t
3
CH0
Starting a Conversion
BIPOLAR (µF)
2.2 || 0.1
2.2 || 0.1
0.01
0.01
NA
0.1
0.1
TRACK
ACQ
). The