MAX1323ECM-T Maxim Integrated, MAX1323ECM-T Datasheet - Page 9

• Manufacturer Part Number: MAX1323ECM-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

PIN
22
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
CONVST
ALLON
NAME
DGND
SHDN
DV
EOLC
REF-
EOC
I.C.2
CLK
D10
D11
D12
D13
_______________________________________________________________________________________
RD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
CS
DD
N eg ati ve Refer ence Byp ass. RE F- i s the b yp ass p oi nt for an i nter nal l y g ener ated r efer ence vol tag e. Byp ass
RE F- w i th a 0.1µF cap aci tor to AG N D . Al so b yp ass RE F- to RE F+ w i th a 2.2µF and a 0.1µF cap aci tor .
Digital Out Bit 0 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital Out Bit 1 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital Out Bit 2 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital Out Bit 3 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital Out Bit 4 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital Out Bit 5 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital Out Bit 6 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital Out Bit 7 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital Out Bit 8 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital Out Bit 9 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital Out Bit 10 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital Out Bit 11 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital Out Bit 12 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital Out Bit 13 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital Supply Input. Apply +2.7V to +5.25V to DV
Digital Supply GND. DGND is the power return for DV
(see the Layout, Grounding, and Bypassing section).
End-of-Conversion Output. EOC goes low to indicate the end of a conversion. EOC returns high after
one clock period.
End-of-Last-Conversion Output. EOLC goes low to indicate the end of the last conversion. EOLC
returns high when CONVST goes low for the next conversion sequence. For the MAX1319/MAX1323/
MAX1327, EOLC gives the same information as EOC.
Read Input. Pulling RD low initiates a read command of the parallel data buses, D0–D13. D0–D13 are
high impedance while either RD or CS is high.
Internally Connected 2. Connect I.C.2 to DV
Chip-Select Input. Pulling CS low activates the digital interface. D0–D13 are high impedance while
either CS or RD is high.
Convert-Start Input. Driving CONVST high places the device in hold mode and initiates the
conversion process. The analog inputs are sampled on the rising edge of CONVST. When CONVST
is low the analog inputs are tracked.
External-Clock Input. CLK accepts an external clock signal up to 15MHz. Connect CLK to DGND for
internally clocked conversions. To select external clock mode, set INTCLK/EXTCLK = 0.
Shutdown Input. Set SHDN = 0 for normal operation. Set SHDN = 1 for shutdown mode.
ALLON is not implemented. Connect ALLON to DGND.
14-Bit, Parallel-Interface ADCs
526ksps, Single-Channel,
DD
FUNCTION
.
DD
Pin Description (continued)
. Bypass DV
DD
. Connect DGND to AGND at only one point
DD
to DGND with a 0.1µF capacitor.
9