LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 198
LPC1113FHN33/303,5
Manufacturer Part Number
LPC1113FHN33/303,5
Description
ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1113FHN333035.pdf
(538 pages)
Specifications of LPC1113FHN33/303,5
Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1113
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
24 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Package / Case
HVQFN-33
Mounting Style
SMD/SMT
Factory Pack Quantity
260
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UM10398
User manual
13.5.7 UART Line Control Register (U0LCR - 0x4000 800C)
Table 191. UART FIFO Control Register (U0FCR - address 0x4000 8008, Write Only) bit
The U0LCR determines the format of the data character that is to be transmitted or
received.
Table 192. UART Line Control Register (U0LCR - address 0x4000 800C) bit description
Bit
0
1
2
3
5:4
7:6
31:8 -
Bit
1:0
2
Symbol Value Description
WLS
SBS
Symbol
FIFOEN
RXFIFORES
TXFIFORES
-
-
RXTL
description
0
1
All information provided in this document is subject to legal disclaimers.
0x0
0x1
0x2
0x3
Value
0
1
0
1
0
1
-
-
Rev. 12 — 24 September 2012
Word Length Select
5-bit character length.
6-bit character length.
7-bit character length.
8-bit character length.
Stop Bit Select
1 stop bit.
2 stop bits (1.5 if U0LCR[1:0]=00).
0x0
0x1
0x2
0x3
Description
FIFO Enable
UART FIFOs are disabled. Must not be used in the
application.
Active high enable for both UART Rx and TX FIFOs and
U0FCR[7:1] access. This bit must be set for proper UART
operation. Any transition on this bit will automatically clear
the UART FIFOs.
RX FIFO Reset
No impact on either of UART FIFOs.
Writing a logic 1 to U0FCR[1] will clear all bytes in UART
Rx FIFO, reset the pointer logic. This bit is self-clearing.
TX FIFO Reset
No impact on either of UART FIFOs.
Writing a logic 1 to U0FCR[2] will clear all bytes in UART
TX FIFO, reset the pointer logic. This bit is self-clearing.
Reserved
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
RX Trigger Level. These two bits determine how many
receiver UART FIFO characters must be written before an
interrupt is activated.
Trigger level 0 (1 character or 0x01).
Trigger level 1 (4 characters or 0x04).
Trigger level 2 (8 characters or 0x08).
Trigger level 3 (14 characters or 0x0E).
Reserved
Chapter 13: LPC111x/LPC11Cxx UART
UM10398
© NXP B.V. 2012. All rights reserved.
198 of 538
Reset
value
0
0
0
0
NA
0
-
Reset
Value
0
0
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