LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 252
LPC1113FHN33/303,5
Manufacturer Part Number
LPC1113FHN33/303,5
Description
ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1113FHN333035.pdf
(538 pages)
Specifications of LPC1113FHN33/303,5
Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1113
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
24 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Package / Case
HVQFN-33
Mounting Style
SMD/SMT
Factory Pack Quantity
260
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NXP Semiconductors
Table 235. Master Transmitter mode
UM10398
User manual
Status
Code
(I2CSTAT
)
0x08
0x10
0x18
0x20
0x28
0x30
0x38
Status of the I
and hardware
A START condition
has been transmitted.
A Repeated START
condition has been
transmitted.
SLA+W has been
transmitted; ACK has
been received.
SLA+W has been
transmitted; NOT ACK
has been received.
Data byte in DAT has
been transmitted;
ACK has been
received.
Data byte in DAT has
been transmitted;
NOT ACK has been
received.
Arbitration lost in
SLA+R/W or Data
bytes.
2
C-bus
Application software response
To/From DAT
Load SLA+W;
clear STA
Load SLA+W or
Load SLA+R;
Clear STA
Load data byte or
No DAT action or
No DAT action or
No DAT action
Load data byte or
No DAT action or
No DAT action or
No DAT action
Load data byte or
No DAT action or
No DAT action or
No DAT action
Load data byte or
No DAT action or
No DAT action or
No DAT action
No DAT action or
No DAT action
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
To CON
STA STO SI
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Next action taken by I
SLA+W will be transmitted; ACK bit will
be received.
As above.
SLA+R will be transmitted; the I
will be switched to MST/REC mode.
Data byte will be transmitted; ACK bit will
be received.
Repeated START will be transmitted.
STOP condition will be transmitted; STO
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
Data byte will be transmitted; ACK bit will
be received.
Repeated START will be transmitted.
STOP condition will be transmitted; STO
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
Data byte will be transmitted; ACK bit will
be received.
Repeated START will be transmitted.
STOP condition will be transmitted; STO
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
Data byte will be transmitted; ACK bit will
be received.
Repeated START will be transmitted.
STOP condition will be transmitted; STO
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
I
slave will be entered.
A START condition will be transmitted
when the bus becomes free.
2
C-bus will be released; not addressed
UM10398
© NXP B.V. 2012. All rights reserved.
2
C hardware
2
C block
252 of 538
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