LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 344
LPC1113FHN33/303,5
Manufacturer Part Number
LPC1113FHN33/303,5
Description
ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1113FHN333035.pdf
(538 pages)
Specifications of LPC1113FHN33/303,5
Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1113
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
24 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Package / Case
HVQFN-33
Mounting Style
SMD/SMT
Factory Pack Quantity
260
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Table 302. Match Control Register (TMR16B0MCR - address 0x4000 C014 and TMR16B1MCR - address 0x4001 0014)
UM10398
User manual
Bit
0
1
2
Symbol Value Description
MR0I
MR0R
MR0S
bit description
19.7.4 Prescale Register (TMR16B0PR - address 0x4000 C00C and
19.7.5 Prescale Counter register (TMR16B0PC - address 0x4000 C010 and
19.7.6 Match Control Register (TMR16B0MCR and TMR16B1MCR)
1
0
1
0
1
0
TMR16B1PR - address 0x4001 000C)
The 16-bit Prescale Register specifies the maximum value for the Prescale Counter.
Table 300: Prescale registers (TMR16B0PR, address 0x4000 C00C and TMR16B1PR
TMR16B1PC - address 0x4001 0010)
The 16-bit Prescale Counter controls division of PCLK by some constant value before it is
applied to the Timer Counter. This allows control of the relationship between the resolution
of the timer and the maximum time before the timer overflows. The Prescale Counter is
incremented on every PCLK. When it reaches the value stored in the Prescale Register,
the Timer Counter is incremented, and the Prescale Counter is reset on the next PCLK.
This causes the TC to increment on every PCLK when PR = 0, every 2 PCLKs when
PR = 1, etc.
Table 301: Prescale counter registers (TMR16B0PC, address 0x4001 C010 and TMR16B1PC
The Match Control Register is used to control what operations are performed when one of
the Match Registers matches the Timer Counter. The function of each of the bits is shown
in
Bit
15:0
31:16
Bit
15:0
31:16
Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
Enabled
Disabled
Reset on MR0: the TC will be reset if MR0 matches it.
Enabled
Disabled
Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches
the TC.
Enabled
Disabled
Table
302.
Symbol
Symbol
PR
-
PC
-
0x4001 000C) bit description
0x4000 0010) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Chapter 19: LPC1100XL series: 16-bit counter/timer CT16B0/1
Description
Prescale max value.
Reserved.
Description
Prescale counter value.
Reserved.
UM10398
© NXP B.V. 2012. All rights reserved.
344 of 538
0
Reset
value
0
0
Reset
value
0
-
Reset
value
0
-
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