LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 400
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LPC1113FHN33/303,5
Manufacturer Part Number
LPC1113FHN33/303,5
Description
ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1113FHN333035.pdf
(538 pages)
Specifications of LPC1113FHN33/303,5
Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1113
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
24 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Package / Case
HVQFN-33
Mounting Style
SMD/SMT
Factory Pack Quantity
260
- Current page: 400 of 538
- Download datasheet (5Mb)
25.1 How to read this chapter
25.2 Basic configuration
25.3 Features
25.4 Pin description
UM10398
User manual
The ADC block is identical for all LPC111x, LPC11D14, and LPC11Cxx parts.
All HVQFN33 and LQFP48 packages support eight ADC channels. On the small
packages (TSSOP28/DIP28/TSSOP20/SO20), only five or six ADC channels are pinned
out (see
The ADC is configured using the following registers:
Remark: Basic clocking for the A/D converters is determined by the APB clock (PCLK). A
programmable divider is included in the A/D converter to scale this clock to the 4.5 MHz
(max) clock needed by the successive approximation process. An accurate conversion
requires 11 clock cycles.
Table 361
1. Pins: The ADC pin functions are configured in the IOCONFIG register block
2. Power and peripheral clock: In the SYSAHBCLKCTRL register, set bit 13
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UM10398
Chapter 25: LPC111x/LPC11Cxx ADC
Rev. 12 — 24 September 2012
(Section
Power to the ADC at run-time is controlled through the PDRUNCFG register
(Table
10-bit successive approximation Analog-to-Digital Converter (ADC).
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 to 3.6 V. Do not exceed the V
10-bit conversion time 2.44 s.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition on input pin or Timer Match signal.
Individual result registers for each A/D channel to reduce interrupt overhead.
Table
gives a brief summary of the ADC related pins.
43).
7.4).
3).
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
DD
voltage level.
© NXP B.V. 2012. All rights reserved.
User manual
(Table
400 of 538
21).
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