Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 111

• Manufacturer Part Number: Z8F041APH020SG2156
• Description: 8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F041APH020SG2156

• Rohs: yes
• Core: eZ8
• Processor Series: Z8F041xx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS022827-1212
Watchdog Timer Refresh
Watchdog Timer Time-Out Response
When first enabled, the Watchdog Timer is loaded with the value in the Watchdog Timer
Reload registers. The Watchdog Timer counts down to
tion is executed by the eZ8 CPU. Execution of the WDT instruction causes the downcoun-
ter to be reloaded with the WDT reload value stored in the Watchdog Timer Reload
registers. Counting resumes following the reload operation.
When the Z8 Encore! XP F082A Series devices are operating in DEBUG Mode (using the
on-chip debugger), the Watchdog Timer is continuously refreshed to prevent any Watch-
dog Timer time-outs.
The Watchdog Timer times out when the counter reaches
Watchdog Timer generates either an interrupt or a system reset. The WDT_RES Flash
option bit determines the time-out response of the Watchdog Timer. For information about
programming the WDT_RES Flash option bit, see the
page 159.
WDT Interrupt in Normal Operation
If configured to generate an interrupt when a time-out occurs, the Watchdog Timer issues
an interrupt request to the interrupt controller and sets the WDT status bit in the Reset Sta-
tus (RSTSTAT) Register; see the
enabled, the eZ8 CPU responds to the interrupt request by fetching the Watchdog Timer
interrupt vector and executing code from the vector address. After time-out and interrupt
generation, the Watchdog Timer counter rolls over to its maximum value of
continues counting. The Watchdog Timer counter is not automatically returned to its
reload value.
The Reset Status (RSTSTAT) Register must be read before clearing the WDT interrupt.
This read clears the WDT time-out Flag and prevents further WDT interrupts from imme-
diately occurring.
WDT Interrupt in STOP Mode
If configured to generate an interrupt when a time-out occurs and the Z8 Encore! XP
F082A Series devices are in STOP Mode, the Watchdog Timer automatically initiates a
Stop Mode Recovery and generates an interrupt request. Both the WDT status bit and the
STOP bit in the Reset Status (RSTSTAT) Register are set to 1 following a WDT time-out
in STOP Mode. For more information about Stop Mode Recovery, see
Mode Recovery and Low Voltage Detection
If interrupts are enabled, following completion of the Stop Mode Recovery the eZ8 CPU
responds to the interrupt request by fetching the Watchdog Timer interrupt vector and exe-
cuting code from the vector address.
P R E L I M I N A R Y
Reset Status Register
chapter on page 22.
Flash Option Bits
000000H
on page 29. If interrupts are
Z8 Encore! XP
000000H
Product Specification
unless a WDT instruc-
. A time-out of the
the Reset, Stop
®
chapter on
F082A Series
FFFFFH
Operation
and
94