Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 131

• Manufacturer Part Number: Z8F041APH020SG2156
• Description: 8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F041APH020SG2156

• Rohs: yes
• Core: eZ8
• Processor Series: Z8F041xx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS022827-1212
Bit
Field
RESET
R/W
Address
Bit
[7]
RDA
[6]
PE
[5]
OE
[4]
FE
[3]
BRKD
UART Status 0 Register
Description
Receive Data Available
This bit indicates that the UART Receive Data Register has received data. Reading the UART
Receive Data Register clears this bit.
0 = The UART Receive Data Register is empty.
1 = There is a byte in the UART Receive Data Register.
Parity Error
This bit indicates that a parity error has occurred. Reading the UART Receive Data Register
clears this bit.
0 = No parity error has occurred.
1 = A parity error has occurred.
Overrun Error
This bit indicates that an overrun error has occurred. An overrun occurs when new data is
received and the UART Receive Data Register has not been read. If the RDA bit is reset to 0,
reading the UART Receive Data Register clears this bit.
0 = No overrun error occurred.
1 = An overrun error occurred.
Framing Error
This bit indicates that a framing error (no Stop bit following data reception) was detected.
Reading the UART Receive Data Register clears this bit.
0 = No framing error occurred.
1 = A framing error occurred.
Break Detect
This bit indicates that a break occurred. If the data bits, parity/multiprocessor bit and Stop bit(s)
are all 0s this bit is set to 1. Reading the UART Receive Data Register clears this bit.
0 = No break occurred.
1 = A break occurred.
RDA
R
7
0
The UART Status 0 (UxSTAT0) and Status 1(UxSTAT1) registers, shown in Tables 65 and
66, identify the current UART operating configuration and status.
PE
R
6
0
Table 65. UART Status 0 Register (U0STAT0)
OE
R
5
0
P R E L I M I N A R Y
FE
R
4
0
F41H
BRKD
R
3
0
Z8 Encore! XP
UART Control Register Definitions
TDRE
R
2
1
Product Specification
TXE
R
1
1
®
F082A Series
CTS
R
X
0
114