Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 144

• Manufacturer Part Number: Z8F041APH020SG2156
• Description: 8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F041APH020SG2156

• Rohs: yes
• Core: eZ8
• Processor Series: Z8F041xx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS022827-1212
Caution:
Continuous Conversion
4. CEN remains 1 while the conversion is in progress. A single-shot conversion requires
5. When the conversion is complete, the ADC control logic performs the following oper-
6. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically
When configured for continuous conversion, the ADC continuously performs an analog-
to-digital conversion on the selected analog input. Each new data value overwrites the pre-
vious value stored in the ADC Data registers. An interrupt is generated after each conver-
sion.
Observe the following steps for setting up the ADC and initiating continuous conversion:
1. Enable the appropriate analog input by configuring the general-purpose I/O pins for
2. Write the ADC Control/Status Register 1 to configure the ADC.
In CONTINUOUS Mode, ADC updates are limited by the input signal bandwidth of the
ADC and the latency of the ADC and its digital filter. Step changes at the input are not
immediately detected at the next output from the ADC. The response of the ADC (in all
modes) is limited by the input signal bandwidth and the latency.
–
–
–
5129 system clock cycles to complete. If a single-shot conversion is requested from an
ADC powered down state, the ADC uses 40 additional clock cycles to power up
before beginning the 5129 cycle conversion.
ations:
–
–
–
powered down.
alternate function. This action disables the digital input and output driver.
If the internal voltage reference must be output to a pin, set the
The internal voltage reference must be enabled in this case.
Write the
voltage reference level or to disable the internal reference. The
contained in the ADC Control/Status Register 1.
Set CEN to 1 to start the conversion.
13-bit two’s-complement result written to {ADCD_H[7:0], ADCD_L[7:3]}
Sends an interrupt request to the Interrupt Controller denoting conversion com-
plete
CEN resets to 0 to indicate the conversion is complete
REFSELL
P R E L I M I N A R Y
bit of the pair {
REFSELH
Z8 Encore! XP
,
REFSELL
Product Specification
} to select the internal
®
REFEXT
F082A Series
REFSELH
Operation
bit to 1.
bit is
127