Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 208

• Manufacturer Part Number: Z8F041APH020SG2156
• Description: 8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F041APH020SG2156

• Rohs: yes
• Core: eZ8
• Processor Series: Z8F041xx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS022827-1212
Bit
[7]
DBGMODE
[6]
BRKEN
Bit
Field
RESET
R/W
On-Chip Debugger Control Register Definitions
OCD Control Register
DBGMODE
Description
DEBUG Mode
The device enters DEBUG Mode when this bit is 1. When in DEBUG Mode, the eZ8 CPU
stops fetching new instructions. Clearing this bit causes the eZ8 CPU to restart. This bit is
automatically set when a BRK instruction is decoded and Breakpoints are enabled. If the
Flash Read Protect Option Bit is enabled, this bit can only be cleared by resetting the
device. It cannot be written to 0.
0 = The Z8 Encore! XP F082A Series device is operating in NORMAL Mode.
1 = The Z8 Encore! XP F082A Series device is in DEBUG Mode.
Breakpoint Enable
This bit controls the behavior of the BRK instruction (opcode 00H). By default, Breakpoints
are disabled and the BRK instruction behaves similar to an NOP instruction. If this bit is 1,
when a BRK instruction is decoded, the DBGMODE bit of the OCDCTL Register is automati-
cally set to 1.
0 = Breakpoints are disabled.
1 = Breakpoints are enabled.
R/W
in DEBUG Mode or the Flash Read Protect Option bit is enabled, this command reads and
discards one byte.
DBG
DBG
This section describes the features of the On-Chip Debugger Control and Status registers.
The OCD Control Register controls the state of the On-Chip Debugger. This register is
used to enter or exit DEBUG Mode and to enable the
Z8 Encore! XP F082A Series device.
A reset and stop function can be achieved by writing
function can be achieved by writing
a run function can be implemented by writing
7
0
←
←
12H
1-5 byte opcode
BRKEN
R/W
6
0
Table 110. OCD Control Register (OCDCTL)
DBGACK
R/W
5
0
P R E L I M I N A R Y
41H
R
4
0
to this register. If the device is in DEBUG Mode,
40H
R
3
0
Reserved
to this register.
81H
BRK
On-Chip Debugger Control Register
Z8 Encore! XP
to this register. A reset and go
instruction. It can also reset the
R
2
0
Product Specification
R
1
0
®
F082A Series
RST
R/W
0
0
191