Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 21
Z8F041APH020SG2156
Manufacturer Part Number
Z8F041APH020SG2156
Description
8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
Manufacturer
ZiLOG
Datasheet
1.Z8F082ASJ020EG2156.pdf
(282 pages)
Specifications of Z8F041APH020SG2156
Rohs
yes
Core
eZ8
Processor Series
Z8F041xx
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
4 KB
Data Ram Size
1 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
PDIP-20
Mounting Style
Through Hole
A/d Bit Size
10 bit
A/d Channels Available
8
Interface Type
UART
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
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PS022827-1212
CPU and Peripheral Overview
10-Bit Analog-to-Digital Converter
Low-Power Operational Amplifier
The eZ8 CPU, Zilog’s latest 8-bit Central Processing Unit (CPU), meets the continuing
demand for faster and more code-efficient microcontrollers. The eZ8 CPU executes a
superset of the original Z8 instruction set. The features of eZ8 CPU include:
For more information about eZ8 CPU, refer to the
(UM0128), which is available for download on www.zilog.com.
The optional analog-to-digital converter (ADC) converts an analog input signal to a 10-bit
binary number. The ADC accepts inputs from eight different analog input pins in both sin-
gle-ended and differential modes. The ADC also features a unity gain buffer when high
input impedance is required.
The optional low-power operational amplifier (LPO) is a general-purpose amplifier pri-
marily targeted for current sense applications. The LPO output may be routed internally to
the ADC or externally to a pin.
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Direct register-to-register architecture allows each register to function as an
accumulator, improving execution time and decreasing the required program
memory
Software stack allows much greater depth in subroutine calls and interrupts than
hardware stacks
Compatible with existing Z8 code
Expanded internal Register File allows access of up to 4 KB
New instructions improve execution efficiency for code developed using higher-
level programming languages, including C
Pipelined instruction fetch and execution
New instructions for improved performance including BIT, BSWAP, BTJ, CPC,
LDC, LDCI, LEA, MULT and SRL
New instructions support 12-bit linear addressing of the Register File
Up to 10 MIPS operation
C-Compiler friendly
2 to 9 clock cycles per instruction
P R E L I M I N A R Y
eZ8 CPU Core User Manual
Z8 Encore! XP
CPU and Peripheral Overview
Product Specification
®
F082A Series
4
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