Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 77

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Z8F041APH020SG2156

Manufacturer Part Number
Z8F041APH020SG2156
Description
8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
Manufacturer
ZiLOG
Datasheet

Specifications of Z8F041APH020SG2156

Rohs
yes
Core
eZ8
Processor Series
Z8F041xx
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
4 KB
Data Ram Size
1 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
PDIP-20
Mounting Style
Through Hole
A/d Bit Size
10 bit
A/d Channels Available
8
Interface Type
UART
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
PS022827-1212
Bit
Field
RESET
R/W
Address
Bit
[7]
[6]
T1I
[5]
T0I
Interrupt Control Register Definitions
Caution:
Interrupt Request 0 Register
Description
Reserved
This bit is reserved and must be programmed to 0.
Timer 1 Interrupt Request
0 = No interrupt request is pending for Timer 1.
1 = An interrupt request from Timer 1 is awaiting service.
Timer 0 Interrupt Request
0 = No interrupt request is pending for Timer 0.
1 = An interrupt request from Timer 0 is awaiting service.
Reserved
R/W
7
0
For all interrupts other than the Watchdog Timer interrupt, the Primary Oscillator Fail
Trap and the Watchdog Oscillator Fail Trap, the interrupt control registers enable individ-
ual interrupts, set interrupt priorities and indicate interrupt requests.
The Interrupt Request 0 (IRQ0) Register, shown in Table 35, stores the interrupt requests
for both vectored and polled interrupts. When a request is presented to the interrupt con-
troller, the corresponding bit in the IRQ0 Register becomes 1. If interrupts are globally
enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8
CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the
Interrupt Request 0 Register to determine if any interrupt requests are pending.
To avoid retriggerings of the Watchdog Timer interrupt after exiting the associated inter-
rupt service routine, Zilog recommends that the service routine continues to read from
the RSTSTAT Register until the WDT bit is cleared as shown in the following example.
CLEARWDT:
LDX r0, RSTSTAT ; read reset status register to clear wdt bit
BTJNZ 5, r0, CLEARWDT
R/W
T1I
6
0
Table 35. Interrupt Request 0 Register (IRQ0)
R/W
T0I
5
0
P R E L I M I N A R Y
U0RXI
R/W
4
0
; loop until bit is cleared
FC0H
U0TXI
R/W
3
0
Interrupt Control Register Definitions
Z8 Encore! XP
Reserved Reserved
R/W
2
0
Product Specification
R/W
1
0
®
F082A Series
ADCI
R/W
0
0
60

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