DS26514G Maxim Integrated, DS26514G Datasheet - Page 142

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

10.4 Framer Register Descriptions
10.4.1 Receive Register Descriptions
See
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Receive CRC-16 Display (RCRCD)
Bit 6: Receive HDLC Reset (RHR). Will reset the receive HDLC controller and flush the receive FIFO. Note that
this bit is a acknowledged reset. The host should set this bit and the DS26514 will clear it once the reset operation
is complete. The DS26514 will complete the HDLC reset within 2 frames.
Bit 5: Receive HDLC Mapping Select (RHMS)
Bits 4 to 0: Receive HDLC Channel Select 4 to 0 (RHCS[4:0]). These bits determine which DS0 is mapped to
the HDLC controller when enabled with RHMS = 0. RHCS[4:0] = all 0s selects channel 1, RHCS[4:0] = all 1s
selects channel 32 (E1). A change to the receive HDLC channel select is acknowledged only after a receive HDLC
reset (RHR).
19-5856; Rev 4; 5/11
Table 10-3
0 = Do not write received CRC-16 code to FIFO (default).
1 = Write received CRC-16 code to FIFO after last octet of packet.
0 = Normal operation.
1 = Reset receive HDLC controller and flush the receive FIFO.
0 = Receive HDLC assigned to channels.
1 = Receive HDLC assigned to FDL (T1 mode), Sa bits (E1 mode).
RCRCD
7
0
for the complete framer register list.
RHC
Receive HDLC Control Register
010h + (200h x (n - 1)) : where n = 1 to 4
RHR
6
0
RHMS
5
0
RHCS4
4
0
RHCS3
3
0
DS26514 4-Port T1/E1/J1 Transceiver
RHCS2
2
0
RHCS1
1
0
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RHCS0
0
0