DS26514G Maxim Integrated, DS26514G Datasheet - Page 32
DS26514G
Manufacturer Part Number
DS26514G
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS26514G.pdf
(305 pages)
Specifications of DS26514G
Part # Aliases
90-26514-G00
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9.2.2 CLKO Output Clock Generation
This clock output is derived from MCLK based upon the setting of the CLKOSEL[2:0] bits in the
register.The reference for the PLL is not the input clock on MCLK, but the scaled version of MCLK (1.544MHz or
2.048MHz). The LTRCR.T1J1E1S bit also selects the proper PLL for use in generating the appropriate frequency.
This clock output pin is provided as an additional feature to eliminate the need for another board oscillator.
Table 9-1. CLKO Frequency Selection
19-5856; Rev 4; 5/11
CLKOSEL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
CLKO (kHz)
16384
12352
12288
2048
4096
8192
1544
3088
6176
1536
3072
6144
128
256
32
64
DS26514 4-Port T1/E1/J1 Transceiver
32 of 305
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