DS26514G Maxim Integrated, DS26514G Datasheet - Page 35
DS26514G
Manufacturer Part Number
DS26514G
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS26514G.pdf
(305 pages)
Specifications of DS26514G
Part # Aliases
90-26514-G00
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DS26514GN+
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DS26514GN+
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Figure 9-10. Device Interrupt Information Flow Diagram
19-5856; Rev 4; 5/11
Receive Remote Alarm Indication Clear
Receive Alarm Condition Clear
Receive Loss of Signal Clear
Receive Loss of Frame Clear
Receive Remote Alarm Indication
Receive Alarm Condition
Receive Loss of Signal
Receive Loss of Frame
Receive Signal All Ones
Receive Signal All Zeros
Receive CRC4 Multiframe
Receive Align Frame
Loss of Receive Clk Clear / Loss of Receive Clk Clear
Spare Code Detected Condition Clear / -
Loop Down Code Clear / V52 Link Clear
Loop Up Code Clear / Receive Distant MF Alarm Clear
Loss of Receive Clk / Loss of Receive Clk
Spare Code Detect / -
Loop Down Detect / V52 Link Detect
Loop Up Detect / Receive Distant MF Alarm Detect
Receive Elastic Store Full
Receive Elastic Store Empty
Receive Elastic Store Slip
Receive Signaling Change of State (Enable in RSCSE1-4)
One Second Timer
Timer
Receive Multiframe
Receive FIFO Overrun
Receive HDLC Opening Byte
Receive Packet End
Receive Packet Start
Receive Packet High Watermark
Receive FIFO Not Empty
Receive RAI-CI
Receive AIS-CI
Receive SLC-96 Alignment
Receive FDL Register Full
Receive BOC Clear
Receive BOC
Transmit Elastic Store Full
Transmit Elastic Store Empty
Transmit Elastic Store Slip
Transmit SLC96 Multiframe
Transmit Multiframe
Loss of Transmit Clock Clear
Loss of Transmit Clock
Transmit FDL Register Empty
Transmit FIFO Underrun
Transmit Message End
Transmit FIFO Below Low Watermark
Transmit FIFO Not Full Set
-
-
Loss of Frame
Loss of Frame Synchronization
Jitter Attenuator Limit Trip Clear
Open Circuit Detect Clear
Short Circuit Detect Clear
Loss of Signal Detect Clear
Jitter Attenuator Limit Trip
Open Circuit Detect
Short Circuit Detect
Loss of Signal Detect
BERT Bit Error Detected
BERT Bit Counter Overflow
BERT Error Counter Overflow
BERT Receive All Ones
BERT Receive All Zeros
BERT Receive Loss of Synchronization
BERT in Synchronization
Transmit Align Frame
7
6
5
4
3
2
1
0
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
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2
1
0
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0
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0
7
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1
0
4
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2
1
0
-
-
1
0
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0
6
5
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0
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1
2
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1
0
Interrupt Status
Interrupt Mask
Registers
Registers
DS26514 4-Port T1/E1/J1 Transceiver
Drawing Legend:
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Register Name
Register Name
35 of 305
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