DS26514G Maxim Integrated, DS26514G Datasheet - Page 58
DS26514G
Manufacturer Part Number
DS26514G
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS26514G.pdf
(305 pages)
Specifications of DS26514G
Part # Aliases
90-26514-G00
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9.9.4.4 Receive SLC-96 Operation (T1 Mode Only)
In an SLC-96-based transmission scheme, the standard Fs-bit pattern is robbed to make room for a set of
message fields. The SLC-96 multiframe is made up of six D4 superframes, hence it is 72 frames long. In the 72-
frame SLC-96 multiframe, 36 of the framing bits are the normal Ft pattern and the other 36-bits are divided into
alarm, maintenance, spoiler, and concentrator bits as well as 12-bits of the normal Fs pattern. Additional SLC-96
information can be found in BellCore document TR-TSY-000008.
To enable the DS26514 to synchronize onto a SLC-96 pattern, the following configuration should be used:
The SLC-96 message bits can be extracted via the T1RSLC1–3 registers. The status bit RSLC96 located at
RLS7.3 is useful for retrieving SLC-96 message data. The RSLC96 bit will indicate when the framer has updated
the data link registers T1RSLC1–3 with the latest message data from the incoming data stream. Once the RSLC96
bit is set, the user will have 9ms (or until the next RSLC96 interrupt) to retrieve the most recent message data from
the T1RSLC1–3 registers. Note that RSLC96 will not set if the DS26514 is unable to detect the 12-bit SLC-96
alignment pattern.
19-5856; Rev 4; 5/11
•
•
•
•
RCR1.5 (RFM) = 1
RCR1.3 (SYNCC) = 1
T1RCR2.4 (RSLC96) = 1
RCR1.7 (SYNCT) = 0
Set to D4 framing mode.
Set to cross-couple Ft and Fs bits.
Enable SLC-96 synchronizer.
Set to minimum sync time.
DS26514 4-Port T1/E1/J1 Transceiver
58 of 305
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