DS26514G Maxim Integrated, DS26514G Datasheet - Page 8

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

DS26514 4-Port T1/E1/J1 Transceiver
Table 10-2. Global Register List ......................................................................................................................... 103
Table 10-3. Framer Register List ........................................................................................................................ 104
Table 10-4. LIU Register List .............................................................................................................................. 111
Table 10-5. BERT Register List .......................................................................................................................... 112
Table 10-6. HDLC-256 Register List ................................................................................................................... 113
Table 10-7. Global Register Bit Map ................................................................................................................... 114
Table 10-8. Framer Register Bit Map ................................................................................................................. 115
Table 10-9. Framer Register Bit Map ................................................................................................................. 115
Table 10-10. LIU Register Bit Map ..................................................................................................................... 124
Table 10-11. BERT Register Bit Map ................................................................................................................. 125
Table 10-12. HDLC-256 Register Bit Map .......................................................................................................... 126
Table 10-13. Global Register Set ....................................................................................................................... 127
Table 10-14. Output Status Control .................................................................................................................... 128
Table 10-15. Master Clock Input Selection ......................................................................................................... 131
Table 10-16. Backplane Reference Clock Select ................................................................................................ 132
Table 10-17. Device ID Codes in this Product Family ......................................................................................... 134
Table 10-18. LIU Register Set ............................................................................................................................ 236
Table 10-19. Transmit Load Impedance Selection .............................................................................................. 238
Table 10-20. Transmit Pulse Shape Selection .................................................................................................... 238
Table 10-21. Receive Level Indication ................................................................................................................ 243
Table 10-22. Receive Impedance Selection ....................................................................................................... 244
Table 10-23. Receiver Sensitivity Selection with Monitor Mode Disabled ............................................................ 245
Table 10-24. Receiver Sensitivity Selection with Monitor Mode Enabled ............................................................. 245
Table 10-25. BERT Register Set ........................................................................................................................ 246
Table 10-26. BERT Pattern Select ..................................................................................................................... 248
Table 10-27. BERT Error Insertion Rate ............................................................................................................. 249
Table 10-28. BERT Repetitive Pattern Length Select ......................................................................................... 249
Table 10-29. Extended BERT Register Set ........................................................................................................ 253
Table 10-30. Transmit Side HDLC-256 Register Map ......................................................................................... 257
Table 10-31. Receive Side HDLC-256 Register Map .......................................................................................... 260
Table 12-1. Recommended DC Operating Conditions ........................................................................................ 283
Table 12-2. Capacitance .................................................................................................................................... 283
Table 12-3. Recommended DC Operating Conditions ........................................................................................ 283
Table 12-4. Thermal Characteristics ................................................................................................................... 284
Table 12-5. Transmitter Characteristics .............................................................................................................. 284
Table 12-6. Receiver Characteristics .................................................................................................................. 284
Table 13-1. SPI Bus Mode Timing ...................................................................................................................... 285
Table 13-2. AC Characteristics—Microprocessor Bus Timing ............................................................................. 287
Table 13-3. Receiver AC Characteristics ............................................................................................................ 290
Table 13-4. Transmit AC Characteristics ............................................................................................................ 293
Table 13-5. JTAG Interface Timing..................................................................................................................... 296
Table 14-1. Instruction Codes for IEEE 1149.1 Architecture ............................................................................... 301
Table 14-2. ID Code Structure ........................................................................................................................... 302
19-5856; Rev 4; 5/11
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