DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 33
DS26524GA4
Manufacturer Part Number
DS26524GA4
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS26524GA4.pdf
(273 pages)
Specifications of DS26524GA4
Part # Aliases
90-26524-GA4
- Current page: 33 of 273
- Download datasheet (2Mb)
8.8.1.4 Receiving Mapped T1 Channels from a 2.048MHz Backplane
Setting the TSCLKM bit (TIOCR.4) enables the transmit elastic store to operate with a 2.048MHz backplane (32
time slots/frame). In this mode the user can choose which of the backplane channels on TSER will be mapped into
the T1 data stream by programming the Transmit Blank Channel Select registers (TBCS1:TBCS4). A logic 1 in the
associated bit location forces the transmit elastic store to ignore backplane data for that channel. Typically the user
will want to program eight channels to be ignored. The default (power-up) configuration ignores channels 25 to 32,
so that the first 24 backplane channels are mapped into the T1 transmit data stream.
For example, if the user desired to transmit data from the 2.048MHz backplane channels 2 to 16 and 18 to 26, the
TBCS1:TBCS4
8.8.1.5 Mapping T1 Channels onto a 2.048MHz Backplane
Setting the RSCLKM bit (RIOCR.4) enables the receive elastic store to operate with a 2.048MHz backplane (32
time slots/frame). In this mode the user can choose which of the backplane channels on RSER receive the T1 data
by programming the Receive Blank Channel Select registers (RBCS1:RBCS4). A logic 1 in the associated bit
location forces RSER high for that backplane channel. Typically the user will want to program eight channels to be
blanked. The default (power-up) configuration blanks channels 25 to 32, so that the 24 T1 channels are mapped
into the first 24 channels of the 2.048MHz backplane. If the user chooses to blank channel 1 (TS0) by setting
RBCS1.0 = 1, the F-bit will be passed into the MSB of TS0 on RSER.
For example, if:
Then on RSER:
Note that when two or more sequential channels are chosen to be blanked, the receive slip zone select bit should
be set to 0. If the blank channels are distributed (such as 1, 5, 9, 13, 17, 21, 25, 29), the RSZS bit can be set to 1,
which can provide a lower occurrence of slips in certain applications.
If the two-frame elastic buffer either fills or empties, a controlled slip occurs. If the buffer empties, a full frame of
data is repeated at RSER and the RLS4.5 and RLS4.6 bits are set to 1. If the buffer fills, a full frame of data is
deleted and the RLS4.5 and RLS4.7 bits are set to 1.
8.8.1.6 Receiving Mapped E1 Transmit Channels from a 1.544MHz Backplane
The user can use the TSCLKM bit in TIOCR.4 to enable the transmit elastic store to operate with a 1.544MHz
backplane (24 channels / frame + F-bit). In this mode the user can choose which of the E1 time slots will have all-
ones data inserted by programming the Transmit Blank Channel Select registers (TBCS1:TBCS4). A logic 1 in the
associated bit location causes the elastic store to force all ones at the outgoing E1 data for that channel. Typically
the user will want to program eight channels to be blanked. The default (power-up) configuration blanks channels
25 to 32, so that the first 24 E1 channels are mapped from the 24 channels of the 1.544MHz backplane.
TBCS1
TBCS2
TBCS3
TBCS4
RBCS1
RBCS2
RBCS3
RBCS4
Channel 1 (MSB) = F-bit
Channel 1 (bits 1 to 7) = all ones
Channels 2 to 16 = T1 channels 1 to 15
Channel 17 = all ones
Channels 18 to 26 = T1 channels 16 to 24
Channels 27 to 32 = all ones
registers should be programmed as follows:
= 01h :: ignore backplane channel 1 ::
= 00h
= 01h :: ignore backplane channel 17 ::
= FCh :: ignore backplane channels 27 to 32 ::
= 01h
= 00h
= 01h
= FCh
33 of 273
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