DS26519GA2 Maxim Integrated, DS26519GA2 Datasheet - Page 300
DS26519GA2
Manufacturer Part Number
DS26519GA2
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS26519GA2.pdf
(310 pages)
Specifications of DS26519GA2
Part # Aliases
90-26519-0A2
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13.2
Table 13-5. JTAG Interface Timing
(V
(See
Note 1:
Note 2:
Figure 13-13. JTAG Interface Timing Diagram
JTCLK Clock Period
JTCLK Clock High:Low Time
JTCLK to JTDI, JTMS Setup Time
JTCLK to JTDI, JTMS Hold Time
JTCLK to JTDO Delay
JTCLK to JTDO High-Impedance Delay
JTRST Width Low Time
DD
= 3.3V ±5%, T
Figure
JTDI, JTMS, JTRST
JTAG Interface Timing
The timing parameters in this table are guaranteed by design (GBD).
Clock can be stopped high or low.
13-13.)
PARAMETER
JTRST
JTCLK
JTD0
A
= 0°C to +70°C for DS26519G; T
t6
t7
t2
SYMBOL
t2:t3
t1
t4
t5
t6
t7
t8
300 of 310
t4
t1
A
t5
(Note 2)
CONDITIONS
= -40°C to +85°C for DS26519GN.) (Note 1)
t3
t8
DS26519 16-Port T1/E1/J1 Transceiver
MIN
100
50
5
2
2
2
1000
TYP
500
MAX
50
50
UNITS
ns
ns
ns
ns
ns
ns
ns
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