72291L15PF IDT, 72291L15PF Datasheet

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... RESET LOGIC PRS IDT, IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES © 2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. ...

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... There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. In IDT Standard mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read ...

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... RCLK can be used to read the offsets in parallel from Qn regardless of whether serial or parallel offset loading has been selected. During Master Reset (MRS) the following events occur: The read and write pointers are set to the first location of the FIFO. The FWFT pin selects IDT WRITE CLOCK (WCLK) WRITE ENABLE (WEN) ...

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... In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to the FIFO memory the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty. In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs. ...

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... COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Parameter Min. Typ. Max. 4.5 5.0 5 2.0 — — — — 0.8 0 — 70 -40 — 85 IDT72281 IDT72291 Commercial & Industrial ( 10, 15 CLK Min. Max. –1 1 –10 10 2.4 — — 0.4 — 80 — 20 Unit °C °C Unit μ ...

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... Skew time between RCLK and WCLK for EF/OR SKEW3 NOTES: 1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Industrial temperature range product for 15ns and 20ns speed grade are available as a standard device. 3. Pulse widths less than minimum values are not allowed. ...

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... When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further write operations reads are performed after a reset, IR will go HIGH after D writes to the FIFO 65,537 writes for the IDT72281 and 131,073 writes for the IDT72291, respectively. Note that the additional word in FWFT mode is due to the capacity of the memory plus output register ...

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... IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE IDT72281 Number of Words 32,768 FIFO 32,769 to (65,536–(m+1)) (65,536–m) 65,536 NOTES Empty Offset, Default Values 127 when parallel offset loading is selected 1,023 when serial offset loading is selected. ...

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... X NOTES: 1. The programming method can only be selected at Master Reset. 2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected. 3. The programming sequence applies to both IDT Standard and FWFT modes. Figure 4. Programmable Flag Offset Programming Sequence ...

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... The act of reading the offset registers employs a dedicated read offset register pointer. The contents of the offset registers can be read on the Q Q pins when LD is set LOW and REN is set LOW. For the IDT72281, data n are read via Q HIGH transition of RCLK. Upon the second LOW-to-HIGH transition of RCLK, data are read from the Empty Offset MSB Register ...

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... D– 2 words should have been written into the FIFO between Reset (Master or Partial) and the time of Retransmit setup 65,536 for the IDT72281 and D = 131,072 for the IDT72291 in IDT Standard mode. In FWFT mode 65,537 for the IDT72281 and D = 131,073 for the IDT72291 ...

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... Retransmit setup is initiated by holding RT LOW during a rising RCLK edge. REN and WEN must be HIGH before bringing RT LOW. If IDT Standard mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting EF LOW. The change in level will only be noticeable if EF was HIGH before setup. During this period, the internal read pointer is initialized to the first location of the RAM array ...

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... IR goes HIGH, inhibiting further write operations reads are performed after a reset (either MRS or PRS), IR will go HIGH after D writes to the FIFO (D = 65,537 for the IDT72281 and 131,073 for the IDT72291) See Figure 9, Write Timing (FWFT Mode), for the relevant timing information ...

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... RCLK edge that accomplishes this condition sets HF HIGH. In IDT Standard mode reads are performed after reset (MRS or PRS), HF will go LOW after (D writes to the FIFO, where D = 65,536 for the IDT72281 and 131,072 for the IDT72291. ...

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... IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF RSS t RSS t t RSS t RSS t RSS If FWFT = HIGH HIGH t RSF If FWFT = LOW LOW t If FWFT = LOW HIGH RSF ...

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... IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS If FWFT = HIGH HIGH t RSF If FWFT = LOW HIGH t RSF If FWFT = HIGH LOW t RSF t RSF t RSF Figure 6. Partial Reset Timing ...

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... WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus t SKEW3 the rising edge of WCLK and the rising edge of RCLK is less than HIGH. Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode) t CLK t ...

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... IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 COMMERCIAL AND INDUSTRIAL 18 TEMPERATURE RANGES ...

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... IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 COMMERCIAL AND INDUSTRIAL 19 TEMPERATURE RANGES ...

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... FIFO after Master Reset more than D – 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 65,536 for the IDT72281 and 131,072 for the IDT72291 goes HIGH RCLK cycle + t . ...

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... OR goes LOW RCLK cycles + t REF WCLK t ENS SEN t LDS BIT 0 NOTE for the IDT72281 and for the IDT72291. Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes x+1 t SKEW2 ENH t REF t ...

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... LDS LDH ENS ENH REN DATA IN OUTPUT REGISTER 0 7 NOTE LOW. Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for the IDT72291 t LDH t ENH t DH PAE OFFSET PAF OFFSET (MSB) (LSB) t LDH t ENH t DH ...

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... REN NOTES: 1. For IDT Standard mode maximum FIFO depth 65,536 for the IDT72281 and 131,072 for the IDT72291. 2. For FWFT mode maximum FIFO depth 65,537 for the IDT72281 and 131,073 for the IDT72291. Figure 20. Half-Full Flag Timing (IDT Standard and FWFT Modes) ...

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... Use an AND gate in IDT Standard mode gate in FWFT mode not connect any output control signals directly together. 3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths. Figure 21. Block Diagram of 65,536 x 18 and 131,072 x 18 Width Expansion by one cycle between FIFOs ...

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... DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72281 can easily be adapted to applications requiring depths greater than 65,536 and 131,072 for the IDT72291 with a 9-bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary. The resulting configuration provides a total depth equivalent to the sum of the depths associated with each single FIFO ...

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... Thin Plastic Quad Flatpack (TQFP, PN64-1) Slim Thin Quad Flatpack (STQFP, PP64-1) Commercial Only Clock Cycle Time (t Com'l & Ind'l Speed in Nanoseconds Com'l & Ind'l Low Power 65,536 x 9 SuperSyncFIFO 131,072 x 9 SuperSyncFIFO 4675 drw26 for Tech Support: 408-360-1753 email: FIFOhelp@idt.com ) CLK ...