74F273PC_Q Fairchild Semiconductor, 74F273PC_Q Datasheet
74F273PC_Q
Specifications of 74F273PC_Q
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74F273PC_Q Summary of contents
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... Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC © 2000 Fairchild Semiconductor Corporation Features Ideal buffer for MOS microprocessor or memory Eight edge-triggered D-type flip-flops ...
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Unit Loading/Fan Out Pin Names D –D Data Inputs Master Reset (Active LOW) CP Clock Pulse Input (Active Rising Edge) Q –Q Data Outputs 0 7 Mode Select-Function Table Operating Mode Reset (Clear) Load “1” Load “0” ...
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Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 2) Input Current (Note 5.0 mA Voltage Applied to Output in HIGH State ...
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AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PLH t Clock to Output PHL t Propagation Delay PLH Output PHL AC Operating Requirements Symbol Parameter t (H) Setup Time, HIGH or LOW ...
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Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 5 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20D 6 ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...