MAX7304ETG+T Maxim Integrated, MAX7304ETG+T Datasheet - Page 12

• Manufacturer Part Number: MAX7304ETG+T
• Description: LED Lighting Drivers I2C 16Port LT GPIO and LED Driver
• Manufacturer: Maxim Integrated

Specifications of MAX7304ETG+T

• Rohs: yes

Each LED driver-supported port has its own blink-control
settings through registers 0x54 to 0x57 (see
in the
from 0 (blink disabled) to 4.096s. Settable blink duty
cycles range from 6.25% to 50%. All blink periods start at
the same PWM cycle for synchronized blinking between
multiple ports.
Each port has its own counter to generate blink
timing. The blink counter can be programmed to cause
the output to gate off and on at a programmable rate. The
blink period can be set to 256ms, 512ms, 1.024s, 2.048s,
or 4.096s using D[4:2] of the port’s individual configura-
tion register. The percentage of time that the LED is on
for one blink cycle is set to 50%, 25%, 12.5%, or 6.25%
by D[1:0] of the individual configuration register.
Two possible sources generate INT: I
GPIOs configured as inputs (registers 0x48, 0x5A, and
0x5B). Read the respective data/status registers for each
type of interrupt in order to clear INT. If multiple sources
generate the interrupt, all the related status registers
must be read to clear INT.
Figure 1. Two-Wire Serial Interface Timing Details
Maxim Integrated
Register Tables
SDA
SCL
t
HD, STA
with High Level of Integrated ESD Protection
CONDITION
START
section). The blink period ranges
t
LOW
Level-Translating GPIO and LED Driver
t
R
t
HIGH
t
SU, DAT
t
F
2
C timeout or
t
HD, DAT
LED Blink
Interrupt
Table 22
t
SU, STA
START CONDITION
Figure 1
The device operates as a slave that sends and receives
data through an I
interface uses a serial-data line (SDA) and a serial-
clock line (SCL) to achieve bidirectional communication
between master(s) and slave(s). A master (typically a
microcontroller) initiates all data transfers to and from the
device and generates the SCL clock that synchronizes
the data transfer.
The device’s SDA line operates as both an input and an
open-drain output. A pullup resistor, typically 4.7kI, is
required on SDA. The device’s SCL line operates only as
an input. A pullup resistor is required on SCL if there are
multiple masters on the 2-wire interface, or if the master
in a single-master system has an open-drain SCL output.
Each transmission consists of a START (S) condition
(Figure
slave address plus R/W bit, a register address byte, one
or more data bytes, and finally, a STOP (P) condition.
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START condition by transitioning SDA from high
to low while SCL is high. When the master has finished
communicating with the slave, it issues a STOP condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
REPEATED
I
2
t
2) sent by a master, followed by the device’s 7-bit
t
HD, STA
R
C-Interfaced 16-Port,
shows the 2-wire serial interface timing details.
2
C-compatible 2-wire interface. The
START and STOP Conditions
t
SU, STO
t
t
F
F
,
TX
CONDITION
Serial Interface
STOP
Serial Addressing
MAX7304
t
BUF
CONDITION
START
12