MAX7304ETG+T Maxim Integrated, MAX7304ETG+T Datasheet - Page 16

• Manufacturer Part Number: MAX7304ETG+T
• Description: LED Lighting Drivers I2C 16Port LT GPIO and LED Driver
• Manufacturer: Maxim Integrated

Specifications of MAX7304ETG+T

• Rohs: yes

The LED’s on-time in each PWM cycle is phase delayed
by 45N into four evenly spaced start positions. Optimize
phasing when using fewer than four ports as constant-
current outputs by allocating the ports with the most
appropriate start positions. For example, if using two
constant-current outputs, choose PORT12 and PORT14
because their PWM start positions are evenly spaced.
In general, choose the ports that spread the current
demand from the ports’ load supply.
The device operates with a 1.62V to 3.6V power-supply
voltage. Bypass the power supply V
0.1FF or higher ceramic capacitor as close as possible
to the device. Bypass the logic power supply (V
GND with a 0.1FF or higher ceramic capacitor as close
as possible to the device.
Table 3. ESD Test Levels
X = Open level. The level has to be specified in the dedicated equipment specification. If higher voltages than those shown are
specified, special test equipment could be needed.
Table 4. ESD Waveform Parameters
Maxim Integrated
LEVEL
1
2
3
4
INDICATED
LEVEL
VOLTAGE
with High Level of Integrated ESD Protection
X
1
2
3
4
(kV)
2
4
6
8
1A—CONTACT DISCHARGE
Power-Supply Considerations
FIRST PEAK OF CURRENT
Level-Translating GPIO and LED Driver
DISCHARGE Q10%
TEST VOLTAGE (kV)
22.5
Staggered PWM
(A)
7.5
15
30
CC
Special
to GND with a
2
4
6
8
LA
) to
DISCHARGE SWITCH
RISE TIME (t
0.7 to 1
0.7 to 1
0.7 to 1
0.7 to 1
All device pins meet the Q2.5kV Human Body Model ESD
tolerances. The GPIOs meet IEC 61000-4-2 ESD protec-
tion. The IEC test stresses consist of 10 consecutive ESD
discharges per polarity at the maximum specified level
and below (per IEC 61000-4-2). Test criteria include:
1) The powered device does not latch up during the ESD
2) The device subsequently passes the final test used for
Tables 3
1999-05: Electromagnetic compatibility (EMC) Testing
and measurement techniques—Electrostatic discharge
immunity test.
(ns)
discharge event.
prescreening.
I
R
2
) WITH
C-Interfaced 16-Port,
LEVEL
and
1
2
3
4
X
4
are from the IEC 61000-4-2: Edition 1.1
1B—AIR DISCHARGE
CURRENT (Q30%)
AT 30ns
(A)
12
16
4
8
TEST VOLTAGE (kV)
MAX7304
ESD Protection
CURRENT (Q30%)
Special
15
2
4
8
AT 60ns
(A)
2
4
6
8
16