Z8F011ASH020EG2156 ZiLOG, Z8F011ASH020EG2156 Datasheet - Page 105

• Manufacturer Part Number: Z8F011ASH020EG2156
• Description: 8-bit Microcontrollers - MCU 1K FLASH 256B RAM 16B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F011ASH020EG2156

• Rohs: yes
• Core: eZ8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 1 KB
• Data Ram Size: 256 B
• On-chip Adc: No
• Package / Case: SOIC-20
• Mounting Style: SMD/SMT
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS025113-1212
Bit
Field
RESET
R/W
Address
Bit
[7]
TMODEHI
[6:5]
TICONFIG
[4]
[3:1]
PWMD
Timer 0–1 Control Registers
TMODEHI
Description
Timer Mode High Bit
This bit along with the TMODE field in the TxCTL1 Register determines the operating mode
of the timer. This is the most significant bit of the timer mode selection value. See the
TxCTL1 Register description on the next page for additional details.
Timer Interrupt Configuration
This field configures timer interrupt definition.
0x = Timer interrupt occurs on all of the defined reload, compare and input events.
10 = Timer interrupt occurs only on defined input capture/deassertion events.
11 = Timer interrupt occurs only on defined reload/compare events.
Reserved
This bit is reserved and must be programmed to 0.
PWM Delay Value
This field is a programmable delay to control the number of system clock cycles delay
before the timer output and the timer output complement are forced to their Active state.
000 = No delay.
001 = 2 cycles delay.
010 = 4 cycles delay.
011 = 8 cycles delay.
100 = 16 cycles delay.
101 = 32 cycles delay.
110 = 64 cycles delay.
111 = 128 cycles delay.
R/W
7
0
The Timer Control registers are 8-bit read/write registers that control the operation of their
associated counter/timers.
Time 0–1 Control Register 0
The Timer Control 0 (TxCTL0) and Timer Control 1 (TxCTL1) registers determine the
timer operating mode. These registers also include a programmable PWM deadband delay,
two bits to configure the timer interrupt definition, and a status bit to identify if the most
recent timer interrupt is caused by an input capture event.
R/W
Table 56. Timer 0–1 Control Register 0 (TxCTL0)
6
0
TICONFIG
R/W
5
0
Reserved
R/W
4
0
F06H, F0EH
R/W
3
0
Timer Control Register Definitions
PWMD
R/W
Z8 Encore!
2
0
Product Specification
R/W
1
0
®
F0830 Series
INPCAP
R/W
0
0
87