Z8F011ASH020EG2156 ZiLOG, Z8F011ASH020EG2156 Datasheet - Page 108

no-image

Z8F011ASH020EG2156

Manufacturer Part Number
Z8F011ASH020EG2156
Description
8-bit Microcontrollers - MCU 1K FLASH 256B RAM 16B NVDS
Manufacturer
ZiLOG
Datasheet

Specifications of Z8F011ASH020EG2156

Rohs
yes
Core
eZ8
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
1 KB
Data Ram Size
256 B
On-chip Adc
No
Package / Case
SOIC-20
Mounting Style
SMD/SMT
Interface Type
UART
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
PS025113-1212
Bit
[6]
TPOL
(cont’d)
[5:3]
PRES
Description (Continued)
PWM DUAL OUTPUT Mode
0 = Timer output is forced Low (0) and timer output complement is forced High (1), when the
1 = Timer output is forced High (1) and timer output complement is forced Low (0) when the
CAPTURE RESTART Mode
0 = Count is captured on the rising edge of the timer input signal.
1 = Count is captured on the falling edge of the timer input signal.
COMPARATOR COUNTER Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When the timer
is enabled, the timer output signal is complemented on timer reload.
Caution: When the timer output alternate function TxOUT on a GPIO port pin is enabled,
TxOUT will change to whatever state the TPOL bit is in. The timer does not need to be enabled
for that to happen. Additionally, the port data direction sub register is not needed to be set to
output on TxOUT. Changing the TPOL bit when the timer is enabled and running does not
immediately change the polarity TxOUT.
Prescale Value
The timer input clock is divided by 2
reset each time the timer is disabled. This reset ensures proper clock division each time the
timer is restarted.
000 = Divide by 1.
001 = Divide by 2.
010 = Divide by 4.
011 = Divide by 8.
100 = Divide by 16.
101 = Divide by 32.
110 = Divide by 64.
111 = Divide by 128.
timer is disabled. When enabled and the PWM count matches, the timer output is forced
High (1) and forced Low (0) when enabled and reloaded. When enabled and the PWM
count matches, the timer output complement is forced Low (0) and forced High (1) when
enabled and reloaded.
timer is disabled. When enabled and the PWM count matches, the timer output is forced
Low (0) and forced High (1) when enabled and reloaded.When enabled and the PWM
count matches, the timer output complement is forced High (1) and forced Low (0) when
enabled and reloaded. The PWMD field in the TxCTL0 register determines an optional
added delay on the assertion (Low to High) transition of both timer output and timer output
complement for deadband generation.
PRES
, where PRES can be set from 0 to 7. The prescaler is
Timer Control Register Definitions
Z8 Encore!
Product Specification
®
F0830 Series
90

Related parts for Z8F011ASH020EG2156