Z8F011ASH020EG2156 ZiLOG, Z8F011ASH020EG2156 Datasheet - Page 96

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Z8F011ASH020EG2156

Manufacturer Part Number
Z8F011ASH020EG2156
Description
8-bit Microcontrollers - MCU 1K FLASH 256B RAM 16B NVDS
Manufacturer
ZiLOG
Datasheet

Specifications of Z8F011ASH020EG2156

Rohs
yes
Core
eZ8
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
1 KB
Data Ram Size
256 B
On-chip Adc
No
Package / Case
SOIC-20
Mounting Style
SMD/SMT
Interface Type
UART
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
PS025113-1212
5. Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing
6. Configure the associated GPIO port pin for the timer input alternate function.
7. Write to the Timer Control Register to enable the timer and initiate counting.
In CAPTURE Mode, the elapsed time between the timer start and the capture event can be
calculated using the following equation:
Capture Elapsed Time (s)
CAPTURE RESTART Mode
In CAPTURE RESTART Mode, the current timer count value is recorded when the
acceptable external timer input transition occurs. The capture count value is written to the
timer PWM High and Low Byte registers. The timer input is the system clock. The TPOL
bit in the Timer Control Register determines whether the capture occurs on a rising edge
or a falling edge of the timer input signal. When the capture event occurs, an interrupt is
generated and the count value in the Timer High and Low Byte registers is reset to
and counting resumes. The INPCAP bit in the TxCTL1 Register is set to indicate that the
timer interrupt has been caused by an input capture event.
If no capture event occurs, the timer counts up to 16-bit compare value stored in the Timer
Reload High and Low Byte registers. Upon reaching the reload value, the timer generates
an interrupt, the count value in the Timer High and Low Byte registers is reset to
and counting resumes. The INPCAP bit in the TxCTL1 Register is cleared to indicate that
the timer interrupt has not been caused by an input capture event.
Observe the following steps for configuring a timer for CAPTURE RESTART Mode and
for initiating the count:
1. Write to the Timer Control Register to:
2. Write to the Timer High and Low Byte registers to set the starting count value (typi-
to the relevant interrupt registers. By default, the timer interrupt is generated for both
input capture and Reload events. If appropriate, configure the timer interrupt to be
generated only at the input capture event or the reload event by setting the TICONFIG
field of the TxCTL1 Register.
cally
Disable the timer
Configure the timer for CAPTURE RESTART Mode; setting the mode also
involves writing to TMODEHI bit in the TxCTL1 Register
Set the prescale value
Set the capture edge (rising or falling) for the timer input
0001H
).
=
-------------------------------------------------------------------------------------------------- -
Capture Value Start Value
System Clock Frequency (Hz)
 Prescale
Z8 Encore!
Product Specification
®
F0830 Series
Operation
0001H
0001H
78

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