C8051F313R Silicon Labs, C8051F313R Datasheet - Page 212

• Manufacturer Part Number: C8051F313R
• Description: 8-bit Microcontrollers - MCU 8KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F313R

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 1.25 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: QFN-28
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 17
• Data Rom Size: 128 B
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 25
• Number Of Timers: 5
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

C8051F310/1/2/3/4/5/6/7
18.3. Watchdog Timer Mode
A programmable watchdog timer (WDT) function is available through the PCA Module 4. The WDT is used
to generate a reset if the time between writes to the WDT update register (PCA0CPH4) exceed a specified
limit. The WDT can be configured and enabled/disabled as needed by software.
With the WDTE bit set in the PCA0MD register, Module 4 operates as a watchdog timer (WDT). The Mod-
ule 4 high byte is compared to the PCA counter high byte; the Module 4 low byte holds the offset to be
used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some
PCA registers are restricted while the Watchdog Timer is enabled.
18.3.1. Watchdog Timer Operation
While the WDT is enabled:
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•
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While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control (CR) will read zero if the WDT is enabled but user
software has not enabled the PCA counter. If a match occurs between PCA0CPH4 and PCA0H while the
WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a write
of any value to PCA0CPH4. Upon a PCA0CPH4 write, PCA0H plus the offset held in PCA0CPL4 is loaded
into PCA0CPH4 (See Figure 18.10).
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PCA counter is forced on.
Writes to PCA0L and PCA0H are not allowed.
PCA clock source bits (CPS2-CPS0) are frozen.
PCA Idle control bit (CIDL) is frozen.
Module 4 is forced into software timer mode.
Writes to the Module 4 mode register (PCA0CPM4) are disabled.
PCA0CPL4
C
D
L
I
Figure 18.10. PCA Module 4 with Watchdog Timer Enabled
W
D
T
E
PCA0MD
W
D
C
L
K
PCA0CPH4
C
P
S
2
Write to
C
P
S
1
C
P
S
0
E
C
F
8-bit Adder
Enable
Adder
Enable
Rev. 1.7
PCA0CPH4
Comparator
PCA0H
8-bit
Match
PCA0L Overflow
Reset