C8051F330DR Silicon Labs, C8051F330DR Datasheet - Page 119

• Manufacturer Part Number: C8051F330DR
• Description: 8-bit Microcontrollers - MCU 8kB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F330DR

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• On-chip Adc: No
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: QFN-20
• Mounting Style: SMD/SMT
• Data Rom Size: 128 B
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

14. Port Input/Output
Digital and analog resources are available through 17 I/O pins. Port pins are organized as two byte-wide
Ports and one 1-bit Port. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog
input; Port pins P0.0 - P1.7 can be assigned to one of the internal digital resources as shown in
Figure 14.3. The designer has complete control over which functions are assigned, limited only by the
number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority
Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port latch,
regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 14.3 and Figure 14.4). The registers XBR0 and XBR1, defined in SFR Definition 14.1 and SFR
Definition 14.2, are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 14.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete
Electrical Specifications for Port I/O are given in Table 14.1 on page 134.
Highest
Priority
Lowest
Priority
SYSCLK
Outputs
SMBus
T0, T1
UART
P0
P1
PCA
CP0
SPI
(P0.0-P0.7)
(P1.0-P1.7)
Figure 14.1. Port I/O Functional Block Diagram
2
4
2
2
4
2
8
8
Rev. 1.7
PnSKIP Registers
XBR0, XBR1,
Crossbar
Decoder
Priority
Digital
C8051F330/1/2/3/4/5
8
8
PnMDIN Registers
PnMDOUT,
Cells
Cells
I/O
I/O
P0
P1
P0.0
P0.7
P1.0
P1.7
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