C8051F330DR Silicon Labs, C8051F330DR Datasheet - Page 62

• Manufacturer Part Number: C8051F330DR
• Description: 8-bit Microcontrollers - MCU 8kB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F330DR

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• On-chip Adc: No
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: QFN-20
• Mounting Style: SMD/SMT
• Data Rom Size: 128 B
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• On-chip Dac: No
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 1500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

8.
C8051F330/1/2/3/4/5 devices include an on-chip programmable voltage comparator, Comparator0, shown
in Figure 8.1.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asyn-
chronous “raw” output (CP0A). The asynchronous CP0A signal is available even when in when the system
clock is not active. This allows the Comparator to operate and generate an output with the device in STOP
mode. When assigned to a Port pin, the Comparator output may be configured as open drain or push-pull
(see
source (see
The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 8.2). The CMX0P1–
CMX0P0 bits select the Comparator0 positive input; the CMX0N1–CMX0N0 bits select the Comparator0
negative input. Important Note About Comparator Inputs: The Port pins selected as comparator inputs
should be configured as analog inputs in their associated Port configuration register, and configured to be
skipped by the Crossbar (for details on Port configuration, see
on page
Section “14.2. Port I/O Initialization” on page
Comparator0
129).
Section “10.5. Comparator0 Reset” on page
CMX0N3
CMX0N2
CMX0N1
CMX0N0
CMX0P3
CMX0P2
CMX0P1
CMX0P0
Figure 8.1. Comparator0 Functional Block Diagram
P0.0
P0.2
P0.4
P0.6
P1.0
P1.2
P1.4
P1.6
P0.1
P0.3
P0.5
P0.7
P1.1
P1.3
P1.5
P1.7
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CP0OUT
CP0EN
CP0RIF
CP0FIF
CP0 +
CP0 -
CP0MD1
CP0MD0
CP0RIE
CP0FIE
Rev. 1.7
+
-
GND
VDD
127). Comparator0 may also be used as a reset
CP0RIF
CP0FIF
Decision
Reset
100).
Tree
Section “14.3. General Purpose Port I/O”
(SYNCHRONIZER)
D
C8051F330/1/2/3/4/5
SET
CLR
Q
Q
0
1
0
1
D
SET
CLR
Q
Q
CP0EN
Crossbar
0
1
EA
0
1
CP0A
Interrupt
CP0
CP0
65