EVAL-ADAU1401AEBZ Analog Devices, EVAL-ADAU1401AEBZ Datasheet
EVAL-ADAU1401AEBZ
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EVAL-ADAU1401AEBZ Summary of contents
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... Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ...
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ADAU1401A TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 Analog Performance .................................................................... 4 Digital Input/Output.................................................................... 5 Power.............................................................................................. 6 Temperature Range ...................................................................... 6 PLL and Oscillator........................................................................ ...
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REVISION HISTORY 11/10—Rev Rev. A Changes to Figure 7 and Table 11 .................................................11 Changes to Figure 37 ......................................................................48 Changes to Figure 38 ......................................................................49 Changes to Figure 39 ......................................................................50 4/10—Revision 0: Initial Version Rev Page 3 of ...
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ADAU1401A SPECIFICATIONS AVDD = 3.3 V, DVDD = 1.8 V, PVDD = 3.3 V, IOVDD = 3.3 V, master clock input = 12.288 MHz, unless otherwise noted. ANALOG PERFORMANCE Specifications are guaranteed at 25°C (ambient). Table 1. Parameter Min ADC ...
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Parameter Min Signal-to-Noise Ratio A-Weighted Dynamic Range A-Weighted 92 Total Harmonic Distortion + Noise Interchannel Gain Mismatch Crosstalk DC Bias 1.4 Gain Error −11 DAC OUTPUTS Number of Channels Resolution Full-Scale Analog Output Signal-to-Noise Ratio A-Weighted Dynamic Range A-Weighted 98 ...
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ADAU1401A POWER Table 4. Parameter SUPPLY VOLTAGE Analog Voltage Digital Voltage PLL Voltage IOVDD Voltage SUPPLY CURRENT Analog Current (AVDD and PVDD) Digital Current (DVDD) Analog Current, Reset Digital Current, Reset DISSIPATION 2 Operation (AVDD, DVDD, PVDD) Reset, All Supplies ...
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DIGITAL TIMING SPECIFICATIONS Table 8. 1 Parameter t MIN MASTER CLOCK 291 MP SERIAL PORT t 40 BIL t 40 BIH t 10 LIS t 10 LIH t 10 SIS ...
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ADAU1401A Digital Timing Diagrams t BIH INPUT_BCLK t BIL t LIS INPUT_LRCLK t SIS SDATA_INx LEFT-JUSTIFIED MSB MODE t SIH SDATA_INx MODE SDATA_INx RIGHT-JUSTIFIED MODE 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 14-BIT CLOCKS (18-BIT DATA) ...
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OUTPUT_BCLK t LOS OUTPUT_LRCLK t SODS t SODM SDATA_OUTx LEFT-JUSTIFIED MSB MODE SDATA_OUTx MODE SDATA_OUTx RIGHT-JUSTIFIED MODE 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 14-BIT CLOCKS (18-BIT DATA) 16-BIT CLOCKS (16-BIT DATA MCLKI RESET ...
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ADAU1401A ABSOLUTE MAXIMUM RATINGS Table 9. Parameter Rating DVDD to Ground 2.2 V AVDD to Ground 4.0 V IOVDD to Ground 4.0 V Digital Inputs DGND − 0.3 V, IOVDD + ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADC_RES SELFBOOT MP4/INPUT_LRCLK MP5/INPUT_BCLK MP1/SDATA_IN1 MP0/SDATA_IN0 Table 11. Pin Function Descriptions Pin No. Mnemonic Type 1, 37, 42 AGND PWR 2 ADC0 A_IN 3 ADC_RES A_IN 4 ADC1 A_IN 5 RESET D_IN 6 SELFBOOT D_IN ...
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ADAU1401A Pin No. Mnemonic Type 14 MP7/SDATA_OUT1 D_IO 15 MP6/SDATA_OUT0/ D_IO TDM_IN 16 MP10/OUTPUT_LRCLK D_IO 17 VDRIVE A_OUT 18 IOVDD PWR 19 MP11 D_IO 20 ADDR1/CDATA/WB D_IN 21 CLATCH/WP D_IO 22 SDA/COUT D_IO 23 SCL/CCLK D_IO 26 MP9/SDATA_OUT3/ D_IO/A_IO AUX_ADC0 ...
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Pin No. Mnemonic Type 38, 39 PLL_MODE0, D_IN PLL_MODE1 40 CM A_OUT 41 FILTD A_OUT 43 VOUT3 A_OUT 44 VOUT2 A_OUT 45 VOUT1 A_OUT 46 VOUT0 A_OUT 47 FILTA A_OUT 1 PWR = power/ground, A_IN = analog input, D_IN = ...
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ADAU1401A TYPICAL PERFORMANCE CHARACTERISTICS 0.20 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0. FREQUENCY (kHz) Figure 8. ADC Pass-Band Filter Response 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 ...
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SYSTEM BLOCK DIAGRAM 18kΩ AUDIO ADC INPUT SIGNALS 18kΩ 18kΩ + 10µF MULTIPURPOSE PIN INTERFACES ADCs DACs 3.3V 475Ω 3.3nF PLL SETTINGS 3MHz TO 25MHz 22pF 100Ω 22pF 3.3V 100nF 100nF 100nF 100nF 10µF 10µ IOVDD PVDD AVDD ...
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... The program and parameter RAMs can be loaded with a custom audio processing signal flow built using the SigmaStudio graphical programming software from Analog Devices, Inc. The values stored in the parameter RAM control individual signal processing blocks, such as equalization filters, dynamics processors, audio delays, and mixer levels ...
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INITIALIZATION This section describes the procedure for properly setting up the ADAU1401A. The following five-step sequence provides an overview of how to initialize the IC: 1. Apply power to the ADAU1401A. 2. Wait for the PLL to lock. 3. Load ...
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ADAU1401A set to 0). Each of these can be turned off by writing the appropriate bits in this register. The ADC power-down mode powers down both ADCs, and each DAC can be powered down individually. The current ...
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VOLTAGE REGULATOR The digital voltage of the ADAU1401A must be set to 1.8 V. The chip includes an on-board voltage regulator that allows the device to be used in systems without an available 1.8 V supply but with an available ...
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ADAU1401A AUDIO ADCs The ADAU1401A has two Σ-Δ ADCs. The signal-to-noise ratio (SNR) of the ADCs is 100 dB, and the THD + N is −83 dB. The stereo audio ADCs are current input; therefore, a voltage- to-current resistor is ...
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AUDIO DACs The ADAU1401A includes four Σ-Δ DACs. The SNR of the DACs is 104 dB, and the THD + N is −90 dB. A full-scale output on the DACs is 0.9 V rms (2.5 V p-p). The DACs are ...
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ADAU1401A CONTROL PORTS The ADAU1401A can operate in one of three control modes control, SPI control, or self-boot (no external controller). The ADAU1401A has both a 4-wire SPI control port and a 2 2-wire I C bus ...
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I C PORT The ADAU1401A supports a 2-wire serial (I microprocessor bus driving multiple peripherals. Two pins— serial data (SDA) and serial clock (SCL)—carry information between the ADAU1401A and the system mode, the ADAU1401A ...
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ADAU1401A SCL SDA START BY MASTER CHIP ADDRESS BYTE SCL (CONTINUED) SDA (CONTINUED) SUBADDRESS BYTE 2 SCL SDA START BY MASTER FRAME 1 CHIP ADDRESS BYTE SCL (CONTINUED) SDA (CONTINUED) FRAME 3 SUBADDRESS ...
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I C Read and Write Operations Figure 22 shows the timing of a single-word write operation. On every ninth clock, the ADAU1401A issues an acknowledge by pulling SDA low. Figure 23 shows the timing of a burst mode write ...
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ADAU1401A SPI PORT 2 By default, the ADAU1401A mode, but it can be put into SPI control mode by pulling CLATCH/WP low three times. The SPI port uses a 4-wire interface, consisting of the CLATCH, CCLK, ...
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SELF-BOOT On power-up, the ADAU1401A can load a program and a set of parameters that have been saved in an external EEPROM. Combined with the auxiliary ADC and the multipurpose pins, this eliminates the need for a microcontroller in the ...
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ADAU1401A The writeback function writes data from the ADAU1401A interface registers to the second page of the self-boot EEPROM, EEPROM Address 0x20 to EEPROM Address 0x3F. Starting at EEPROM Address 0x1A (so that the interface register data begins at EEPROM ...
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... DSP core control register. The part can be easily programmed using SigmaStudio (see Figure 30), a graphical tool provided by Analog Devices. No knowledge of writing line-level DSP code is required. More information about SigmaStudio can be found at www.analog.com. ...
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ADAU1401A RAMS AND REGISTERS Table 21. RAM Map and Read/Write Modes Memory Size Parameter RAM 1024 × 32 Program RAM 1024 × Internal registers should be cleared first to prevent clicks and pops. ADDRESS MAPS Table 21 shows ...
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Table 22. Parameter RAM Read/Write Format (Single Address) Byte 0 Byte 1 CHIP_ADR[6:0], W/R 000000, PARAM_ADR[9:8] Table 23. Parameter RAM Block Read/Write Format (Burst Mode) Byte 0 Byte 1 000000, PARAM_ADR[9:8] CHIP_ADR[6:0], W/R Table 24. Program RAM Read/Write Format (Single ...
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ADAU1401A CONTROL REGISTER MAP Blank cells within Table 32 indicate that control bits do not exist in the corresponding locations. Table 32. Register Map MSB No. Register of Address D31 D30 D29 D28 D27 D26 D25 D24 Byte Hex Dec ...
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MSB No. Register of Address D31 D30 D29 D28 D27 D26 D25 D24 Byte s Name Hex Dec D15 D14 D13 D12 D11 D10 D9 0x081C 2076 2 DSP core control RSVD RSVD GD1 GD0 RSVD RSVD RSVD AACW GPCW ...
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... IF[27:0] Interface register 28-bit parameter be saved in these registers are selected in the graphical programming tools. These registers are updated with their corresponding parameter RAM data once per sample period. An edge, which can be set to be either rising or falling, triggers the ADAU1401A to write the current contents of the interface registers to the EEPROM ...
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ADDRESS 2056 (0x0808)—GPIO PIN SETTING REGISTER This register allows the user to set the GPIO pins through the control port. High or low settings can be directly written to or Table 35. GPIO Pin Setting Register Bit Map D15 D14 ...
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ADAU1401A ADDRESS 2057 TO ADDRESS 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS These registers hold the data generated by the 4-channel auxiliary ADC. The ADCs have eight bits of precision and can be extended to 12 bits if filtering is ...
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ADDRESS 2064 TO ADDRESS 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS Many applications require real-time microcontroller control of signal processing parameters, such as filter coefficients, mixer gains, multichannel virtualizing parameters, or dynamics processing curves. When controlling a biquad filter, for example, ...
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ADAU1401A ADDRESS 2074 AND ADDRESS 2075 (0x081A AND 0x081B)—DATA CAPTURE REGISTERS The ADAU1401A data capture feature allows the data at any node in the signal processing flow to be sent to one of two readable registers. This feature is useful ...
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ADDRESS 2076 (0x081C)—DSP CORE CONTROL REGISTER Table 46. DSP Core Control Register Bit Map D15 D14 D13 D12 D11 RSVD RSVD GD1 GD0 RSVD Table 47. DSP Core Control Register Bit Descriptions Bit Name Description GD[1:0] GPIO debounce control. Sets ...
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ADAU1401A ADDRESS 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER Table 48. Serial Output Control Register Bit Map D15 D14 D13 D12 D11 D10 0 0 OLRP OBP M/S OBF1 Table 49. Serial Output Control Register Bit Descriptions Bit Name Description OLRP OUTPUT_LRCLK ...
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... Figure 36 shows an example of a TDM stream running with a pulse word clock, which is used to interface to Analog Devices codecs in auxiliary mode. To work in this mode with either the input or output serial ports, set the ADAU1401A to begin the frame on the rising edge of LRCLK, to change data on the falling edge of BCLK, and to delay the MSB position from the start of the word clock by one BCLK ...
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ADAU1401A ADDRESS 2080 AND ADDRESS 2081 (0x0820 AND 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS Each multipurpose pin can be set to different functions from these registers (Address 2080 and Address 2081). The two 3-byte registers are broken up into 12 4-bit (nibble) ...
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ADDRESS 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL REGISTER Table 55. Auxiliary ADC and Power Control Register Bit Map D15 D14 D13 D12 D11 RSVD RSVD RSVD RSVD RSVD Table 56. Auxiliary ADC and Power Control Register Bit Descriptions Bit Name ...
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ADAU1401A MULTIPURPOSE PINS The ADAU1401A has 12 multipurpose (MP) pins that can be individually programmed to be used as serial data inputs, serial data outputs, digital control inputs to and outputs from the SigmaDSP core, or inputs to the 4-channel ...
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The valid data formats are left-justified, right-justified (24-/20-/18-/16-bit), and 8-channel TDM. In all modes except for the right-justified modes, the serial port accepts an arbitrary number of bits ...
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ADAU1401A LEFT CHANNEL LRCLK BCLK SDATA MSB LRCLK LEFT CHANNEL BCLK MSB SDATA LEFT CHANNEL LRCLK BCLK SDATA MSB LRCLK BCLK SDATA LRCLK BCLK MSB TDM SDATA CH 0 SLOT 0 SLOT 1 32 BCLKs MSB LSB ...
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LAYOUT RECOMMENDATIONS PARTS PLACEMENT The ADC input voltage-to-current resistors and the ADC current set resistor should be placed as close as possible to the 2, 3, and 4 input pins. All 100 nF bypass capacitors, which are recommended for every ...
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ADAU1401A TYPICAL APPLICATION SCHEMATICS SELF-BOOT MODE U1 ADAU1401A Figure 37. Self-Boot Mode Schematic Rev Page ...
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I C CONTROL U1 ADAU1401A 2 Figure 38 Control Schematic Rev Page ADAU1401A ...
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ADAU1401A SPI CONTROL U1 ADAU1401A Figure 39. SPI Control Schematic Rev Page ...
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... VIEW A 0.50 COPLANARITY BSC LEAD PITCH COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 40. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters Package Description 48-Lead LQFP 48-Lead LQFP in 13” Tape and Reel Evaluation Board Rev Page ADAU1401A 37 36 7.20 7. 0.27 0.22 0.17 Package Option ...
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... ADAU1401A NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08506-0-11/10(A) Rev Page ...