MT46V32M16TG-6T IT:F TR Micron Technology Inc, MT46V32M16TG-6T IT:F TR Datasheet - Page 85
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MT46V32M16TG-6T IT:F TR
Manufacturer Part Number
MT46V32M16TG-6T IT:F TR
Description
IC DDR SDRAM 512MBIT 6NS 66TSOP
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V32M16P-5BF_TR.pdf
(91 pages)
Specifications of MT46V32M16TG-6T IT:F TR
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
512M (32Mx16)
Speed
6ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
-40°C ~ 85°C
Package / Case
66-TSOP
Organization
32Mx16
Density
512Mb
Address Bus
15b
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
195mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Figure 50:
PRECHARGE
Auto Precharge
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN
Data Input Timing
Notes:
DQS
1. WRITE command issued at T0.
2.
3.
4. For x16, LDQS controls the lower byte and UDQS controls the upper byte.
5. DI b = data-in from column b.
The bank(s) will be available for a subsequent row access a specified time (
PRECHARGE command is issued, except in the case of concurrent auto precharge. With
concurrent auto precharge, a READ or WRITE command to a different bank is allowed as
long as it does not interrupt the data transfer in the current bank and does not violate
any other timing parameters. Input A10 determines whether one or all banks are to be
precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1
select the bank. When all banks are to be precharged, BA0, BA1 are treated as “Don’t
Care.” Once a bank has been precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to that bank. A PRECHARGE
command will be treated as a NOP if there is no open row in that bank (idle state), or if
the previously open row is already in the process of precharging.
Auto precharge is a feature which performs the same individual-bank precharge func-
tion described above, but without requiring an explicit command. This is accomplished
by using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst.
Auto precharge is either enabled or disabled for each individual READ or WRITE
command. This device supports concurrent auto precharge if the command to the other
bank does not interrupt the data transfer to the current bank.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. This “earliest valid stage” is determined as if an explicit PRECHARGE command
was issued at the earliest possible time, without violating
each burst type in “Operations” on page 52. The user must not issue another command
to the same bank until the precharge time (
DM
CK#
DQ
CK
t
t
DSH (MIN) generally occurs during
DSS (MIN) generally occurs during
T0
1
t DQSS
t WPRES
t DS
t WPRE
DI
T1
b
t DSH 2
t DH
85
T1n
t DQSL
t DSS 3
t
Transitioning Data
t
DQSS (MAX).
DQSS (MIN).
T2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t DQSH
t DSH 2
t
T2n
RP) is completed.
t WPST
t DSS 3
512Mb: x4, x8, x16 DDR SDRAM
T3
Don’t Care
t
RAS (MIN), as described for
©2000 Micron Technology, Inc. All rights reserved.
Operations
t
RP) after the