MT46V64M16P-75:A TR Micron Technology Inc, MT46V64M16P-75:A TR Datasheet - Page 73
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MT46V64M16P-75:A TR
Manufacturer Part Number
MT46V64M16P-75:A TR
Description
IC DDR SDRAM 1GBIT 7.5NS 66TSOP
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V256M4P-6TA_TR.pdf
(82 pages)
Specifications of MT46V64M16P-75:A TR
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
1G (64M x 16)
Speed
7.5ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOP
Organization
64Mx16
Density
1Gb
Address Bus
16b
Access Time (max)
750ps
Maximum Clock Rate
266MHz
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
250mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 45:
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
Command
Address
t DQSS (NOM)
t DQSS (MIN)
t DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
WRITE-to-PRECHARGE – Odd Number of Data, Interrupting
Notes:
Bank a,
WRITE
Col b
T0
t DQSS
t DQSS
t DQSS
1. DI b = data-in for column b.
2. An interrupted burst of 8 is shown; one data element is written.
3.
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T4 and T4n (nominal case) to register DM.
6. If the burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
t
WR is referenced from the first positive CK edge after the last data-in pair.
DI
b
NOP
DI
T1
b
DI
b
T1n
NOP
T2
T2n
73
t WR
NOP
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3n
(a or all)
Bank,
PRE
T4
1Gb: x4, x8, x16 DDR SDRAM
T4n
Transitioning Data
T5
NOP
©2003 Micron Technology, Inc. All rights reserved.
t RP
Operations
T6
NOP
Don’t Care