UPD44324365F5-E40-EQ2 Renesas Electronics America, UPD44324365F5-E40-EQ2 Datasheet - Page 14

• Manufacturer Part Number: UPD44324365F5-E40-EQ2
• Description: SRAM QDRII 36MBIT 165-PBGA
• Manufacturer: Renesas Electronics America

Specifications of UPD44324365F5-E40-EQ2

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 36M (1M x 36)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Truth Table
Remarks 1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.
14
WRITE cycle
Load address, input write data on two
consecutive K and K# rising edge
READ cycle
Load address, read data on two
consecutive C and C# rising edge
NOP (No operation)
Clock stop
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges
3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most
Operation
except if C and C# are HIGH then Data outputs are delivered at K and K# rising edges.
K. All control inputs are registered during the rising edge of K.
rapid restart by overcoming transmission line charging symmetrically.
LD# R, W#
μ
H
X
L
L
PD44324085-A, 44324095-A, 44324185-A, 44324365-A
H
L
X
X
Data Sheet M19873EJ1V0DS
Stopped
L → H
L → H
L → H
CLK
D = X, Q = High-Z
Previous state
Data out
Data in
D or Q
Output clock
Output data
Input clock
Input data
C#(t+1) ↑
K(t+1) ↑
Q(A+0)
D(A+0)
K#(t+1) ↑
C(t+2) ↑
D(A+1)
Q(A+1)