MT46V16M8P-6T IT:D TR Micron Technology Inc, MT46V16M8P-6T IT:D TR Datasheet - Page 71
![IC DDR SDRAM 128MBIT 6NS 66TSOP](/photos/7/22/72288/mfg557-66-tsop_sml.jpg)
MT46V16M8P-6T IT:D TR
Manufacturer Part Number
MT46V16M8P-6T IT:D TR
Description
IC DDR SDRAM 128MBIT 6NS 66TSOP
Manufacturer
Micron Technology Inc
Datasheet
1.MT46V16M8TG-6T_LD_TR.pdf
(81 pages)
Specifications of MT46V16M8P-6T IT:D TR
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
128M (16M x 8)
Speed
6ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
-40°C ~ 85°C
Package / Case
66-TSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 44:
PDF: 09005aef816fd013/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN
COMMAND
ADDRESS
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
WRITE-to-PRECHARGE – Interrupting
CK
Notes:
Bank a,
WRITE
Col b
T0
t
t
t
DQSS
DQSS
DQSS
1. DI b = data-in for column b.
2. Subsequent element of data-in is applied in the programmed order following DI b.
3. An interrupted burst of 8 is shown; two data elements are written.
4.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. DQS is required at T4 and T4n (nominal case) to register DM.
7. If the burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
t
WR is referenced from the first positive CK edge after the last data-in pair.
DI
b
NOP
T1
DI
b
DI
b
T1n
NOP
T2
T2n
71
t
WR
T3
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3n
128Mb: x4, x8, x16 DDR SDRAM
(a or all)
Bank,
T4
PRE
DON’T CARE
T4n
©2004 Micron Technology, Inc. All rights reserved.
T5
NOP
TRANSITIONING DATA
t
RP
Operations
T6
NOP
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